View ST7787_4468277.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

st sitronix ST7787 262k color single-chip tft controller/driver sitronix technology corp. reserves the right to chan ge the contents in this document without prior noti ce. 1 1. introduction the ST7787 is a single-chip controller/driver for 26 2k-color, graphic type tft-lcd. it consists of 720 source line and 320 gate line driving circuits. this chip is capabl e of connecting directly to an external microproces sor, and accepts serial peripheral interface (spi), 8-bits/9-bits/16-bits/18-b its parallel interface. display data can be stored in the on-chip display data ram of 240x320x18 bits. it can perform display data ram read/write operation with no external oper ation clock to minimize power consumption. in addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fe west components. 2. features single chip tft-lcd controller/driver with display data ram display resolution: 240(h) x rgb x 320(v) display data ram (frame memory): 240 x 320 x 18-bit s = 1,382,400 bits operation frequency: dc~30mhz (30mhz for 6 bits, 1 0mhz for 18 bits) output: - 240ch source outputs (240rgb) - 320ch gate outputs - common electrode output display mode (color mode) - full color mode (idle mode off): 262k-colors - reduce color mode (idle mode on): 8-colors (1-bit for individual r, g, b color depth) display resolution option - 240 x 320 display with 240 x 18-bits x 320 displa y ram supported lc type option - mva lc type (when lcm[1]=0,lcm[0]=0 ) - transflective lc type (when lcm[1]=0,lcm[0]=1 ) - transmissive lc type (when lcm[1]=1,lcm[0]=0 ) supported data format on display host interface - 12-bits/pixel: rgb= (444) using the 1382k bits fra me memory and lut - 16-bits/pixel: rgb= (565) using the 1382k bits fra me memory and lut - 18-bits/pixel: rgb= (666) using the 1382k bits fra me memory supported mcu interface - 3-line serial interface - 8-bits, 9-bits, 16-bits, 18-bits interface with 8 080-series mcu - 8-bits, 9-bits, 16-bits, 18-bits interface with 6 800-series mcu - 6-bits, 16-bits, 18-bits rgb interface with graphi c controller display features - area scrolling - partial display mode - software programmable color depth mode build-in circuit - dc/dc converter - adjustable vcom generation - non-volatile (nv) memory to store initial register setting - oscillator for display clock generation - timing controller - 4 preset gamma curve for =1.0/1.8/2.2/2.5 (supporting transflective) and 1 p reset gamma curve for =2.2 (supporting mva, ttransmissive type lc) - factory default value (contrast, module id, modul e version, etc) are stored in nv memory - line inversion, frame inversion nv memory - 8-bits for id1 - 7-bits for id2 - 8-bits for id3 - 8-bits for vcom adjustment supply voltage range - analog supply voltage range (vdd to agnd): 2.45v C 3. 3v - i/o supply voltage range (vddi to dgnd): 1.65v C 3. 3v
ST7787 v1.7 2008.04.18 2 output voltage level - source output voltage range (gvdd to agnd): 3.0v to 5 .0v - power supply range for driver circuit (avdd to agnd) : 5.2v (vdd=2.6v) to 6.0v (vdd=3.0v) - output range of high level of vcom (vcomh to agnd): 2.5v to 5.0v - output range of low level of vcom (vcoml to agnd): - 2.5v to 0.0v - output range of high level of gate driver (vgh to agnd): +12v to +16.5v - output range of low level of gate driver (vgl to ag nd): -14v to C5v lower power consumption, suitable for battery oper ated systems - cmos compatible inputs - optimized layout for cog assembly - operate temperature range: -30 to + 70
ST7787 v1.7 2008.04.18 3 3. pad arrangement dummy dummy vgh vgh vgho vgho vghs c23n c23n c23n c23n gvdd gvdd gvdd dummy dummy dummy s720 s719 s718 s2 s1 dummy g1 dummy dummy dummy dummy dummy g319 g317 g3 s3 g2 g4 dummy dummy g320 g318 c12n c12n c12n c12n c12n c12n vcom vcom vcom vcom vcom vcom vcom vcom dummy dummy dummy dummy dummy dummy vpp vpp vpp vpp vcoml vcoml vcoml vcoml vcoml vcoml vcoml vcoml vcomh vcomh vcomh vcomh vcomh vcomh vcomh vcomh dummy dummy dummy dummy vgl vgl vgl vgl vgls dummy dummy c23p c23p c23p c23p c22n c22n c22n c22n c22p c22p c22p c22p c21n c21n c21n c21n c21p c21p c21p c21p vcl vcl vcl vclo vclo vcls dummy dummy agnd agnd agnd agnd agnd agnd agnd agnd dummy dummy c12p c12p c12p c12p c12p c12p c11n c11n c11n c11n c11n c11n c11p c11p c11p c11p c11p c11p c1so c1so vc1s vc1s vc1s vc1s avdd avdd avdd avdd avdd avdd avdd avddo avddo avdds vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd agnd agnd agnd agnd agnd agnd agnd agnd vci1 vci1 vci1 vci1 dummy dummy vcc vcc vcc vcc vcc vcc regp regpt vref vref vref vddi vddi vddi vddi dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vs hs de dgnd pclk dgnd d/cx dgnd resx auto dummy sda wrx rdx csx te osc tpo0 tpo1 tpo2 tpo3 tpo4 tpo5 tpo6 tpo7 d7 d6 d5 d4 d3 d2 d1 d0 dummy test_en dgndo d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 tp0 tp1 tp2 tp3 vddio lcm1 lcm0 gs dgndo shut vddio tb dgndo rl vddio rev dgndo idm vddio smy dgndo smx vddio srgb dgndo rcm1 vddio rcm0 dgndo p68 vddio im2 dgndo im1 vddio im0 dgndo extc dummy dummy view point: bump view chip size (um): 19384 x 1170 pad coordinate: pad center coordinate origin: chip center chip thickness (um): 300 bump height (um): 15 bump hardness (hv): 75 25 pad arrangement (unit: um): output: pad no. 1 ~ 1069 = 16 x 97 20 18 97 45 16 20 18 97 45 16 input: pad no. 1070 ~ 1335 = 55 x 110 alignment mark (unit: um): (-9533,-248.77) (9544,-248.77)
ST7787 v1.7 2008.04.18 4 4. pad center coordinates pad no. pin name x y pad no. pin name x y 1 dummy 9612 486.72 41 g250 8892 486.72 2 dummy 9594 344.72 42 g248 8874 344.72 3 dummy 9576 486.72 43 g246 8856 486.72 4 dummy 9558 344.72 44 g244 8838 344.72 5 dummy 9540 486.72 45 g242 8820 486.72 6 g320 9522 344.72 46 g240 8802 344.72 7 g318 9504 486.72 47 g238 8784 486.72 8 g316 9486 344.72 48 g236 8766 344.72 9 g314 9468 486.72 49 g234 8748 486.72 10 g312 9450 344.72 50 g232 8730 344.72 11 g310 9432 486.72 51 g230 8712 486.72 12 g308 9414 344.72 52 g228 8694 344.72 13 g306 9396 486.72 53 g226 8676 486.72 14 g304 9378 344.72 54 g224 8658 344.72 15 g302 9360 486.72 55 g222 8640 486.72 16 g300 9342 344.72 56 g220 8622 344.72 17 g298 9324 486.72 57 g218 8604 486.72 18 g296 9306 344.72 58 g216 8586 344.72 19 g294 9288 486.72 59 g214 8568 486.72 20 g292 9270 344.72 60 g212 8550 344.72 21 g290 9252 486.72 61 g210 8532 486.72 22 g288 9234 344.72 62 g208 8514 344.72 23 g286 9216 486.72 63 g206 8496 486.72 24 g284 9198 344.72 64 g204 8478 344.72 25 g282 9180 486.72 65 g202 8460 486.72 26 g280 9162 344.72 66 g200 8442 344.72 27 g278 9144 486.72 67 g198 8424 486.72 28 g276 9126 344.72 68 g196 8406 344.72 29 g274 9108 486.72 69 g194 8388 486.72 30 g272 9090 344.72 70 g192 8370 344.72 31 g270 9072 486.72 71 g190 8352 486.72 32 g268 9054 344.72 72 g188 8334 344.72 33 g266 9036 486.72 73 g186 8316 486.72 34 g264 9018 344.72 74 g184 8298 344.72 35 g262 9000 486.72 75 g182 8280 486.72 36 g260 8982 344.72 76 g180 8262 344.72 37 g258 8964 486.72 77 g178 8244 486.72 38 g256 8946 344.72 78 g176 8226 344.72 39 g254 8928 486.72 79 g174 8208 486.72 40 g252 8910 344.72 80 g172 8190 344.72
ST7787 v1.7 2008.04.18 5 pad no. pin name x y pad no. pin name x y 81 g170 8172 486.72 121 g90 7452 486.72 82 g168 8154 344.72 122 g88 7434 344.72 83 g166 8136 486.72 123 g86 7416 486.72 84 g164 8118 344.72 124 g84 7398 344.72 85 g162 8100 486.72 125 g82 7380 486.72 86 g160 8082 344.72 126 g80 7362 344.72 87 g158 8064 486.72 127 g78 7344 486.72 88 g156 8046 344.72 128 g76 7326 344.72 89 g154 8028 486.72 129 g74 7308 486.72 90 g152 8010 344.72 130 g72 7290 344.72 91 g150 7992 486.72 131 g70 7272 486.72 92 g148 7974 344.72 132 g68 7254 344.72 93 g146 7956 486.72 133 g66 7236 486.72 94 g144 7938 344.72 134 g64 7218 344.72 95 g142 7920 486.72 135 g62 7200 486.72 96 g140 7902 344.72 136 g60 7182 344.72 97 g138 7884 486.72 137 g58 7164 486.72 98 g136 7866 344.72 138 g56 7146 344.72 99 g134 7848 486.72 139 g54 7128 486.72 100 g132 7830 344.72 140 g52 7110 344.72 101 g130 7812 486.72 141 g50 7092 486.72 102 g128 7794 344.72 142 g48 7074 344.72 103 g126 7776 486.72 143 g46 7056 486.72 104 g124 7758 344.72 144 g44 7038 344.72 105 g122 7740 486.72 145 g42 7020 486.72 106 g120 7722 344.72 146 g40 7002 344.72 107 g118 7704 486.72 147 g38 6984 486.72 108 g116 7686 344.72 148 g36 6966 344.72 109 g114 7668 486.72 149 g34 6948 486.72 110 g112 7650 344.72 150 g32 6930 344.72 111 g110 7632 486.72 151 g30 6912 486.72 112 g108 7614 344.72 152 g28 6894 344.72 113 g106 7596 486.72 153 g26 6876 486.72 114 g104 7578 344.72 154 g24 6858 344.72 115 g102 7560 486.72 155 g22 6840 486.72 116 g100 7542 344.72 156 g20 6822 344.72 117 g98 7524 486.72 157 g18 6804 486.72 118 g96 7506 344.72 158 g16 6786 344.72 119 g94 7488 486.72 159 g14 6768 486.72 120 g92 7470 344.72 160 g12 6750 344.72
ST7787 v1.7 2008.04.18 6 pad no. pin name x y pad no. pin name x y 161 g10 6732 486.72 201 s691 6012 486.72 162 g8 6714 344.72 202 s690 5994 344.72 163 g6 6696 486.72 203 s689 5976 486.72 164 g4 6678 344.72 204 s688 5958 344.72 165 g2 6660 486.72 205 s687 5940 486.72 166 dummy 6642 344.72 206 s686 5922 344.72 167 dummy 6624 486.72 207 s685 5904 486.72 168 dummy 6606 344.72 208 s684 5886 344.72 169 dummy 6588 486.72 209 s683 5868 486.72 170 dummy 6570 344.72 210 s682 5850 344.72 171 dummy 6552 486.72 211 s681 5832 486.72 172 s720 6534 344.72 212 s680 5814 344.72 173 s719 6516 486.72 213 s679 5796 486.72 174 s718 6498 344.72 214 s678 5778 344.72 175 s717 6480 486.72 215 s677 5760 486.72 176 s716 6462 344.72 216 s676 5742 344.72 177 s715 6444 486.72 217 s675 5724 486.72 178 s714 6426 344.72 218 s674 5706 344.72 179 s713 6408 486.72 219 s673 5688 486.72 180 s712 6390 344.72 220 s672 5670 344.72 181 s711 6372 486.72 221 s671 5652 486.72 182 s710 6354 344.72 222 s670 5634 344.72 183 s709 6336 486.72 223 s669 5616 486.72 184 s708 6318 344.72 224 s668 5598 344.72 185 s707 6300 486.72 225 s667 5580 486.72 186 s706 6282 344.72 226 s666 5562 344.72 187 s705 6264 486.72 227 s665 5544 486.72 188 s704 6246 344.72 228 s664 5526 344.72 189 s703 6228 486.72 229 s663 5508 486.72 190 s702 6210 344.72 230 s662 5490 344.72 191 s701 6192 486.72 231 s661 5472 486.72 192 s700 6174 344.72 232 s660 5454 344.72 193 s699 6156 486.72 233 s659 5436 486.72 194 s698 6138 344.72 234 s658 5418 344.72 195 s697 6120 486.72 235 s657 5400 486.72 196 s696 6102 344.72 236 s656 5382 344.72 197 s695 6084 486.72 237 s655 5364 486.72 198 s694 6066 344.72 238 s654 5346 344.72 199 s693 6048 486.72 239 s653 5328 486.72 200 s692 6030 344.72 240 s652 5310 344.72
ST7787 v1.7 2008.04.18 7 pad no. pin name x y pad no. pin name x y 241 s651 5292 486.72 281 s611 4572 486.72 242 s650 5274 344.72 282 s610 4554 344.72 243 s649 5256 486.72 283 s609 4536 486.72 244 s648 5238 344.72 284 s608 4518 344.72 245 s647 5220 486.72 285 s607 4500 486.72 246 s646 5202 344.72 286 s606 4482 344.72 247 s645 5184 486.72 287 s605 4464 486.72 248 s644 5166 344.72 288 s604 4446 344.72 249 s643 5148 486.72 289 s603 4428 486.72 250 s642 5130 344.72 290 s602 4410 344.72 251 s641 5112 486.72 291 s601 4392 486.72 252 s640 5094 344.72 292 s600 4374 344.72 253 s639 5076 486.72 293 s599 4356 486.72 254 s638 5058 344.72 294 s598 4338 344.72 255 s637 5040 486.72 295 s597 4320 486.72 256 s636 5022 344.72 296 s596 4302 344.72 257 s635 5004 486.72 297 s595 4284 486.72 258 s634 4986 344.72 298 s594 4266 344.72 259 s633 4968 486.72 299 s593 4248 486.72 260 s632 4950 344.72 300 s592 4230 344.72 261 s631 4932 486.72 301 s591 4212 486.72 262 s630 4914 344.72 302 s590 4194 344.72 263 s629 4896 486.72 303 s589 4176 486.72 264 s628 4878 344.72 304 s588 4158 344.72 265 s627 4860 486.72 305 s587 4140 486.72 266 s626 4842 344.72 306 s586 4122 344.72 267 s625 4824 486.72 307 s585 4104 486.72 268 s624 4806 344.72 308 s584 4086 344.72 269 s623 4788 486.72 309 s583 4068 486.72 270 s622 4770 344.72 310 s582 4050 344.72 271 s621 4752 486.72 311 s581 4032 486.72 272 s620 4734 344.72 312 s580 4014 344.72 273 s619 4716 486.72 313 s579 3996 486.72 274 s618 4698 344.72 314 s578 3978 344.72 275 s617 4680 486.72 315 s577 3960 486.72 276 s616 4662 344.72 316 s576 3942 344.72 277 s615 4644 486.72 317 s575 3924 486.72 278 s614 4626 344.72 318 s574 3906 344.72 279 s613 4608 486.72 319 s573 3888 486.72 280 s612 4590 344.72 320 s572 3870 344.72
ST7787 v1.7 2008.04.18 8 pad no. pin name x y pad no. pin name x y 321 s571 3852 486.72 361 s531 3132 486.72 322 s570 3834 344.72 362 s530 3114 344.72 323 s569 3816 486.72 363 s529 3096 486.72 324 s568 3798 344.72 364 s528 3078 344.72 325 s567 3780 486.72 365 s527 3060 486.72 326 s566 3762 344.72 366 s526 3042 344.72 327 s565 3744 486.72 367 s525 3024 486.72 328 s564 3726 344.72 368 s524 3006 344.72 329 s563 3708 486.72 369 s523 2988 486.72 330 s562 3690 344.72 370 s522 2970 344.72 331 s561 3672 486.72 371 s521 2952 486.72 332 s560 3654 344.72 372 s520 2934 344.72 333 s559 3636 486.72 373 s519 2916 486.72 334 s558 3618 344.72 374 s518 2898 344.72 335 s557 3600 486.72 375 s517 2880 486.72 336 s556 3582 344.72 376 s516 2862 344.72 337 s555 3564 486.72 377 s515 2844 486.72 338 s554 3546 344.72 378 s514 2826 344.72 339 s553 3528 486.72 379 s513 2808 486.72 340 s552 3510 344.72 380 s512 2790 344.72 341 s551 3492 486.72 381 s511 2772 486.72 342 s550 3474 344.72 382 s510 2754 344.72 343 s549 3456 486.72 383 s509 2736 486.72 344 s548 3438 344.72 384 s508 2718 344.72 345 s547 3420 486.72 385 s507 2700 486.72 346 s546 3402 344.72 386 s506 2682 344.72 347 s545 3384 486.72 387 s505 2664 486.72 348 s544 3366 344.72 388 s504 2646 344.72 349 s543 3348 486.72 389 s503 2628 486.72 350 s542 3330 344.72 390 s502 2610 344.72 351 s541 3312 486.72 391 s501 2592 486.72 352 s540 3294 344.72 392 s500 2574 344.72 353 s539 3276 486.72 393 s499 2556 486.72 354 s538 3258 344.72 394 s498 2538 344.72 355 s537 3240 486.72 395 s497 2520 486.72 356 s536 3222 344.72 396 s496 2502 344.72 357 s535 3204 486.72 397 s495 2484 486.72 358 s534 3186 344.72 398 s494 2466 344.72 359 s533 3168 486.72 399 s493 2448 486.72 360 s532 3150 344.72 400 s492 2430 344.72
ST7787 v1.7 2008.04.18 9 pad no. pin name x y pad no. pin name x y 401 s491 2412 486.72 441 s451 1692 486.72 402 s490 2394 344.72 442 s450 1674 344.72 403 s489 2376 486.72 443 s449 1656 486.72 404 s488 2358 344.72 444 s448 1638 344.72 405 s487 2340 486.72 445 s447 1620 486.72 406 s486 2322 344.72 446 s446 1602 344.72 407 s485 2304 486.72 447 s445 1584 486.72 408 s484 2286 344.72 448 s444 1566 344.72 409 s483 2268 486.72 449 s443 1548 486.72 410 s482 2250 344.72 450 s442 1530 344.72 411 s481 2232 486.72 451 s441 1512 486.72 412 s480 2214 344.72 452 s440 1494 344.72 413 s479 2196 486.72 453 s439 1476 486.72 414 s478 2178 344.72 454 s438 1458 344.72 415 s477 2160 486.72 455 s437 1440 486.72 416 s476 2142 344.72 456 s436 1422 344.72 417 s475 2124 486.72 457 s435 1404 486.72 418 s474 2106 344.72 458 s434 1386 344.72 419 s473 2088 486.72 459 s433 1368 486.72 420 s472 2070 344.72 460 s432 1350 344.72 421 s471 2052 486.72 461 s431 1332 486.72 422 s470 2034 344.72 462 s430 1314 344.72 423 s469 2016 486.72 463 s429 1296 486.72 424 s468 1998 344.72 464 s428 1278 344.72 425 s467 1980 486.72 465 s427 1260 486.72 426 s466 1962 344.72 466 s426 1242 344.72 427 s465 1944 486.72 467 s425 1224 486.72 428 s464 1926 344.72 468 s424 1206 344.72 429 s463 1908 486.72 469 s423 1188 486.72 430 s462 1890 344.72 470 s422 1170 344.72 431 s461 1872 486.72 471 s421 1152 486.72 432 s460 1854 344.72 472 s420 1134 344.72 433 s459 1836 486.72 473 s419 1116 486.72 434 s458 1818 344.72 474 s418 1098 344.72 435 s457 1800 486.72 475 s417 1080 486.72 436 s456 1782 344.72 476 s416 1062 344.72 437 s455 1764 486.72 477 s415 1044 486.72 438 s454 1746 344.72 478 s414 1026 344.72 439 s453 1728 486.72 479 s413 1008 486.72 440 s452 1710 344.72 480 s412 990 344.72
ST7787 v1.7 2008.04.18 10 pad no. pin name x y pad no. pin name x y 481 s411 972 486.72 521 s371 252 486.72 482 s410 954 344.72 522 s370 234 344.72 483 s409 936 486.72 523 s369 216 486.72 484 s408 918 344.72 524 s368 198 344.72 485 s407 900 486.72 525 s367 180 486.72 486 s406 882 344.72 526 s366 162 344.72 487 s405 864 486.72 527 s365 144 486.72 488 s404 846 344.72 528 s364 126 344.72 489 s403 828 486.72 529 s363 108 486.72 490 s402 810 344.72 530 s362 90 344.72 491 s401 792 486.72 531 s361 72 486.72 492 s400 774 344.72 532 dummy 54 344.72 493 s399 756 486.72 533 dummy 36 486.72 494 s398 738 344.72 534 dummy 18 344.72 495 s397 720 486.72 535 dummy 0 486.72 496 s396 702 344.72 536 dummy -18 344.72 497 s395 684 486.72 537 dummy -36 486.72 498 s394 666 344.72 538 dummy -54 344.72 499 s393 648 486.72 539 s360 -72 486.72 500 s392 630 344.72 540 s359 -90 344.715 501 s391 612 486.72 541 s358 -108 486.72 502 s390 594 344.72 542 s357 -126 344.715 503 s389 576 486.72 543 s356 -144 486.72 504 s388 558 344.72 544 s355 -162 344.715 505 s387 540 486.72 545 s354 -180 486.72 506 s386 522 344.72 546 s353 -198 344.715 507 s385 504 486.72 547 s352 -216 486.72 508 s384 486 344.72 548 s351 -234 344.715 509 s383 468 486.72 549 s350 -252 486.72 510 s382 450 344.72 550 s349 -270 344.715 511 s381 432 486.72 551 s348 -288 486.72 512 s380 414 344.72 552 s347 -306 344.715 513 s379 396 486.72 553 s346 -324 486.72 514 s378 378 344.72 554 s345 -342 344.715 515 s377 360 486.72 555 s344 -360 486.72 516 s376 342 344.72 556 s343 -378 344.715 517 s375 324 486.72 557 s342 -396 486.72 518 s374 306 344.72 558 s341 -414 344.715 519 s373 288 486.72 559 s340 -432 486.72 520 s372 270 344.72 560 s339 -450 344.715
ST7787 v1.7 2008.04.18 11 pad no. pin name x y pad no. pin name x y 561 s338 -468 486.72 601 s298 -1188 486.72 562 s337 -486 344.715 602 s297 -1206 344.715 563 s336 -504 486.72 603 s296 -1224 486.72 564 s335 -522 344.715 604 s295 -1242 344.715 565 s334 -540 486.72 605 s294 -1260 486.72 566 s333 -558 344.715 606 s293 -1278 344.715 567 s332 -576 486.72 607 s292 -1296 486.72 568 s331 -594 344.715 608 s291 -1314 344.715 569 s330 -612 486.72 609 s290 -1332 486.72 570 s329 -630 344.715 610 s289 -1350 344.715 571 s328 -648 486.72 611 s288 -1368 486.72 572 s327 -666 344.715 612 s287 -1386 344.715 573 s326 -684 486.72 613 s286 -1404 486.72 574 s325 -702 344.715 614 s285 -1422 344.715 575 s324 -720 486.72 615 s284 -1440 486.72 576 s323 -738 344.715 616 s283 -1458 344.715 577 s322 -756 486.72 617 s282 -1476 486.72 578 s321 -774 344.715 618 s281 -1494 344.715 579 s320 -792 486.72 619 s280 -1512 486.72 580 s319 -810 344.715 620 s279 -1530 344.715 581 s318 -828 486.72 621 s278 -1548 486.72 582 s317 -846 344.715 622 s277 -1566 344.715 583 s316 -864 486.72 623 s276 -1584 486.72 584 s315 -882 344.715 624 s275 -1602 344.715 585 s314 -900 486.72 625 s274 -1620 486.72 586 s313 -918 344.715 626 s273 -1638 344.715 587 s312 -936 486.72 627 s272 -1656 486.72 588 s311 -954 344.715 628 s271 -1674 344.715 589 s310 -972 486.72 629 s270 -1692 486.72 590 s309 -990 344.715 630 s269 -1710 344.715 591 s308 -1008 486.72 631 s268 -1728 486.72 592 s307 -1026 344.715 632 s267 -1746 344.715 593 s306 -1044 486.72 633 s266 -1764 486.72 594 s305 -1062 344.715 634 s265 -1782 344.715 595 s304 -1080 486.72 635 s264 -1800 486.72 596 s303 -1098 344.715 636 s263 -1818 344.715 597 s302 -1116 486.72 637 s262 -1836 486.72 598 s301 -1134 344.715 638 s261 -1854 344.715 599 s300 -1152 486.72 639 s260 -1872 486.72 600 s299 -1170 344.715 640 s259 -1890 344.715
ST7787 v1.7 2008.04.18 12 pad no. pin name x y pad no. pin name x y 641 s258 -1908 486.72 681 s218 -2628 486.72 642 s257 -1926 344.715 682 s217 -2646 344.715 643 s256 -1944 486.72 683 s216 -2664 486.72 644 s255 -1962 344.715 684 s215 -2682 344.715 645 s254 -1980 486.72 685 s214 -2700 486.72 646 s253 -1998 344.715 686 s213 -2718 344.715 647 s252 -2016 486.72 687 s212 -2736 486.72 648 s251 -2034 344.715 688 s211 -2754 344.715 649 s250 -2052 486.72 689 s210 -2772 486.72 650 s249 -2070 344.715 690 s209 -2790 344.715 651 s248 -2088 486.72 691 s208 -2808 486.72 652 s247 -2106 344.715 692 s207 -2826 344.715 653 s246 -2124 486.72 693 s206 -2844 486.72 654 s245 -2142 344.715 694 s205 -2862 344.715 655 s244 -2160 486.72 695 s204 -2880 486.72 656 s243 -2178 344.715 696 s203 -2898 344.715 657 s242 -2196 486.72 697 s202 -2916 486.72 658 s241 -2214 344.715 698 s201 -2934 344.715 659 s240 -2232 486.72 699 s200 -2952 486.72 660 s239 -2250 344.715 700 s199 -2970 344.715 661 s238 -2268 486.72 701 s198 -2988 486.72 662 s237 -2286 344.715 702 s197 -3006 344.715 663 s236 -2304 486.72 703 s196 -3024 486.72 664 s235 -2322 344.715 704 s195 -3042 344.715 665 s234 -2340 486.72 705 s194 -3060 486.72 666 s233 -2358 344.715 706 s193 -3078 344.715 667 s232 -2376 486.72 707 s192 -3096 486.72 668 s231 -2394 344.715 708 s191 -3114 344.715 669 s230 -2412 486.72 709 s190 -3132 486.72 670 s229 -2430 344.715 710 s189 -3150 344.715 671 s228 -2448 486.72 711 s188 -3168 486.72 672 s227 -2466 344.715 712 s187 -3186 344.715 673 s226 -2484 486.72 713 s186 -3204 486.72 674 s225 -2502 344.715 714 s185 -3222 344.715 675 s224 -2520 486.72 715 s184 -3240 486.72 676 s223 -2538 344.715 716 s183 -3258 344.715 677 s222 -2556 486.72 717 s182 -3276 486.72 678 s221 -2574 344.715 718 s181 -3294 344.715 679 s220 -2592 486.72 719 s180 -3312 486.72 680 s219 -2610 344.715 720 s179 -3330 344.715
ST7787 v1.7 2008.04.18 13 pad no. pin name x y pad no. pin name x y 721 s178 -3348 486.72 761 s138 -4068 486.72 722 s177 -3366 344.715 762 s137 -4086 344.715 723 s176 -3384 486.72 763 s136 -4104 486.72 724 s175 -3402 344.715 764 s135 -4122 344.715 725 s174 -3420 486.72 765 s134 -4140 486.72 726 s173 -3438 344.715 766 s133 -4158 344.715 727 s172 -3456 486.72 767 s132 -4176 486.72 728 s171 -3474 344.715 768 s131 -4194 344.715 729 s170 -3492 486.72 769 s130 -4212 486.72 730 s169 -3510 344.715 770 s129 -4230 344.715 731 s168 -3528 486.72 771 s128 -4248 486.72 732 s167 -3546 344.715 772 s127 -4266 344.715 733 s166 -3564 486.72 773 s126 -4284 486.72 734 s165 -3582 344.715 774 s125 -4302 344.715 735 s164 -3600 486.72 775 s124 -4320 486.72 736 s163 -3618 344.715 776 s123 -4338 344.715 737 s162 -3636 486.72 777 s122 -4356 486.72 738 s161 -3654 344.715 778 s121 -4374 344.715 739 s160 -3672 486.72 779 s120 -4392 486.72 740 s159 -3690 344.715 780 s119 -4410 344.715 741 s158 -3708 486.72 781 s118 -4428 486.72 742 s157 -3726 344.715 782 s117 -4446 344.715 743 s156 -3744 486.72 783 s116 -4464 486.72 744 s155 -3762 344.715 784 s115 -4482 344.715 745 s154 -3780 486.72 785 s114 -4500 486.72 746 s153 -3798 344.715 786 s113 -4518 344.715 747 s152 -3816 486.72 787 s112 -4536 486.72 748 s151 -3834 344.715 788 s111 -4554 344.715 749 s150 -3852 486.72 789 s110 -4572 486.72 750 s149 -3870 344.715 790 s109 -4590 344.715 751 s148 -3888 486.72 791 s108 -4608 486.72 752 s147 -3906 344.715 792 s107 -4626 344.715 753 s146 -3924 486.72 793 s106 -4644 486.72 754 s145 -3942 344.715 794 s105 -4662 344.715 755 s144 -3960 486.72 795 s104 -4680 486.72 756 s143 -3978 344.715 796 s103 -4698 344.715 757 s142 -3996 486.72 797 s102 -4716 486.72 758 s141 -4014 344.715 798 s101 -4734 344.715 759 s140 -4032 486.72 799 s100 -4752 486.72 760 s139 -4050 344.715 800 s99 -4770 344.715
ST7787 v1.7 2008.04.18 14 pad no. pin name x y pad no. pin name x y 801 s98 -4788 486.72 841 s58 -5508 486.72 802 s97 -4806 344.715 842 s57 -5526 344.715 803 s96 -4824 486.72 843 s56 -5544 486.72 804 s95 -4842 344.715 844 s55 -5562 344.715 805 s94 -4860 486.72 845 s54 -5580 486.72 806 s93 -4878 344.715 846 s53 -5598 344.715 807 s92 -4896 486.72 847 s52 -5616 486.72 808 s91 -4914 344.715 848 s51 -5634 344.715 809 s90 -4932 486.72 849 s50 -5652 486.72 810 s89 -4950 344.715 850 s49 -5670 344.715 811 s88 -4968 486.72 851 s48 -5688 486.72 812 s87 -4986 344.715 852 s47 -5706 344.715 813 s86 -5004 486.72 853 s46 -5724 486.72 814 s85 -5022 344.715 854 s45 -5742 344.715 815 s84 -5040 486.72 855 s44 -5760 486.72 816 s83 -5058 344.715 856 s43 -5778 344.715 817 s82 -5076 486.72 857 s42 -5796 486.72 818 s81 -5094 344.715 858 s41 -5814 344.715 819 s80 -5112 486.72 859 s40 -5832 486.72 820 s79 -5130 344.715 860 s39 -5850 344.715 821 s78 -5148 486.72 861 s38 -5868 486.72 822 s77 -5166 344.715 862 s37 -5886 344.715 823 s76 -5184 486.72 863 s36 -5904 486.72 824 s75 -5202 344.715 864 s35 -5922 344.715 825 s74 -5220 486.72 865 s34 -5940 486.72 826 s73 -5238 344.715 866 s33 -5958 344.715 827 s72 -5256 486.72 867 s32 -5976 486.72 828 s71 -5274 344.715 868 s31 -5994 344.715 829 s70 -5292 486.72 869 s30 -6012 486.72 830 s69 -5310 344.715 870 s29 -6030 344.715 831 s68 -5328 486.72 871 s28 -6048 486.72 832 s67 -5346 344.715 872 s27 -6066 344.715 833 s66 -5364 486.72 873 s26 -6084 486.72 834 s65 -5382 344.715 874 s25 -6102 344.715 835 s64 -5400 486.72 875 s24 -6120 486.72 836 s63 -5418 344.715 876 s23 -6138 344.715 837 s62 -5436 486.72 877 s22 -6156 486.72 838 s61 -5454 344.715 878 s21 -6174 344.715 839 s60 -5472 486.72 879 s20 -6192 486.72 840 s59 -5490 344.715 880 s19 -6210 344.715
ST7787 v1.7 2008.04.18 15 pad no. pin name x y pad no. pin name x y 881 s18 -6228 486.72 921 g33 -6948 486.72 882 s17 -6246 344.715 922 g35 -6966 344.72 883 s16 -6264 486.72 923 g37 -6984 486.72 884 s15 -6282 344.715 924 g39 -7002 344.72 885 s14 -6300 486.72 925 g41 -7020 486.72 886 s13 -6318 344.715 926 g43 -7038 344.72 887 s12 -6336 486.72 927 g45 -7056 486.72 888 s11 -6354 344.715 928 g47 -7074 344.72 889 s10 -6372 486.72 929 g49 -7092 486.72 890 s9 -6390 344.715 930 g51 -7110 344.72 891 s8 -6408 486.72 931 g53 -7128 486.72 892 s7 -6426 344.715 932 g55 -7146 344.72 893 s6 -6444 486.72 933 g57 -7164 486.72 894 s5 -6462 344.715 934 g59 -7182 344.72 895 s4 -6480 486.72 935 g61 -7200 486.72 896 s3 -6498 344.715 936 g63 -7218 344.72 897 s2 -6516 486.72 937 g65 -7236 486.72 898 s1 -6534 344.715 938 g67 -7254 344.72 899 dummy -6552 486.72 939 g69 -7272 486.72 900 dummy -6570 344.72 940 g71 -7290 344.72 901 dummy -6588 486.72 941 g73 -7308 486.72 902 dummy -6606 344.72 942 g75 -7326 344.72 903 dummy -6624 486.72 943 g77 -7344 486.72 904 dummy -6642 344.72 944 g79 -7362 344.72 905 g1 -6660 486.72 945 g81 -7380 486.72 906 g3 -6678 344.72 946 g83 -7398 344.72 907 g5 -6696 486.72 947 g85 -7416 486.72 908 g7 -6714 344.72 948 g87 -7434 344.72 909 g9 -6732 486.72 949 g89 -7452 486.72 910 g11 -6750 344.72 950 g91 -7470 344.72 911 g13 -6768 486.72 951 g93 -7488 486.72 912 g15 -6786 344.72 952 g95 -7506 344.72 913 g17 -6804 486.72 953 g97 -7524 486.72 914 g19 -6822 344.72 954 g99 -7542 344.72 915 g21 -6840 486.72 955 g101 -7560 486.72 916 g23 -6858 344.72 956 g103 -7578 344.72 917 g25 -6876 486.72 957 g105 -7596 486.72 918 g27 -6894 344.72 958 g107 -7614 344.72 919 g29 -6912 486.72 959 g109 -7632 486.72 920 g31 -6930 344.72 960 g111 -7650 344.72
ST7787 v1.7 2008.04.18 16 pad no. pin name x y pad no. pin name x y 961 g113 -7668 486.72 1001 g193 -8388 486.72 962 g115 -7686 344.72 1002 g195 -8406 344.72 963 g117 -7704 486.72 1003 g197 -8424 486.72 964 g119 -7722 344.72 1004 g199 -8442 344.72 965 g121 -7740 486.72 1005 g201 -8460 486.72 966 g123 -7758 344.72 1006 g203 -8478 344.72 967 g125 -7776 486.72 1007 g205 -8496 486.72 968 g127 -7794 344.72 1008 g207 -8514 344.72 969 g129 -7812 486.72 1009 g209 -8532 486.72 970 g131 -7830 344.72 1010 g211 -8550 344.72 971 g133 -7848 486.72 1011 g213 -8568 486.72 972 g135 -7866 344.72 1012 g215 -8586 344.72 973 g137 -7884 486.72 1013 g217 -8604 486.72 974 g139 -7902 344.72 1014 g219 -8622 344.72 975 g141 -7920 486.72 1015 g221 -8640 486.72 976 g143 -7938 344.72 1016 g223 -8658 344.72 977 g145 -7956 486.72 1017 g225 -8676 486.72 978 g147 -7974 344.72 1018 g227 -8694 344.72 979 g149 -7992 486.72 1019 g229 -8712 486.72 980 g151 -8010 344.72 1020 g231 -8730 344.72 981 g153 -8028 486.72 1021 g233 -8748 486.72 982 g155 -8046 344.72 1022 g235 -8766 344.72 983 g157 -8064 486.72 1023 g237 -8784 486.72 984 g159 -8082 344.72 1024 g239 -8802 344.72 985 g161 -8100 486.72 1025 g241 -8820 486.72 986 g163 -8118 344.72 1026 g243 -8838 344.72 987 g165 -8136 486.72 1027 g245 -8856 486.72 988 g167 -8154 344.72 1028 g247 -8874 344.72 989 g169 -8172 486.72 1029 g249 -8892 486.72 990 g171 -8190 344.72 1030 g251 -8910 344.72 991 g173 -8208 486.72 1031 g253 -8928 486.72 992 g175 -8226 344.72 1032 g255 -8946 344.72 993 g177 -8244 486.72 1033 g257 -8964 486.72 994 g179 -8262 344.72 1034 g259 -8982 344.72 995 g181 -8280 486.72 1035 g261 -9000 486.72 996 g183 -8298 344.72 1036 g263 -9018 344.72 997 g185 -8316 486.72 1037 g265 -9036 486.72 998 g187 -8334 344.72 1038 g267 -9054 344.72 999 g189 -8352 486.72 1039 g269 -9072 486.72 1000 g191 -8370 344.72 1040 g271 -9090 344.72
ST7787 v1.7 2008.04.18 17 pad no. pin name x y pad no. pin name x y 1041 g273 -9108 486.72 1081 dgndo -8705 -450.28 1042 g275 -9126 344.72 1082 rcm0 -8625 -450.28 1043 g277 -9144 486.72 1083 vddio -8545 -450.28 1044 g279 -9162 344.72 1084 rcm1 -8465 -450.28 1045 g281 -9180 486.72 1085 dgndo -8385 -450.28 1046 g283 -9198 344.72 1086 srgb -8305 -450.28 1047 g285 -9216 486.72 1087 vddio -8225 -450.28 1048 g287 -9234 344.72 1088 smx -8145 -450.28 1049 g289 -9252 486.72 1089 dgndo -8065 -450.28 1050 g291 -9270 344.72 1090 smy -7985 -450.28 1051 g293 -9288 486.72 1091 vddio -7905 -450.28 1052 g295 -9306 344.72 1092 idm -7825 -450.28 1053 g297 -9324 486.72 1093 dgndo -7745 -450.28 1054 g299 -9342 344.72 1094 rev -7665 -450.28 1055 g301 -9360 486.72 1095 vddio -7585 -450.28 1056 g303 -9378 344.72 1096 rl -7505 -450.28 1057 g305 -9396 486.72 1097 dgndo -7425 -450.28 1058 g307 -9414 344.72 1098 tb -7345 -450.28 1059 g309 -9432 486.72 1099 vddio -7265 -450.28 1060 g311 -9450 344.72 1100 shut -7185 -450.28 1061 g313 -9468 486.72 1101 dgndo -7105 -450.28 1062 g315 -9486 344.72 1102 gs -7025 -450.28 1063 g317 -9504 486.72 1103 lcm1 -6945 -450.28 1064 g319 -9522 344.72 1104 lcm0 -6865 -450.28 1065 dummy -9540 486.72 1105 vddio -6785 -450.28 1066 dummy -9558 344.72 1106 tp0 -6705 -450.28 1067 dummy -9576 486.72 1107 tp1 -6625 -450.28 1068 dummy -9594 344.72 1108 tp2 -6545 -450.28 1069 dummy -9612 486.72 1109 tp3 -6465 -450.28 1070 dummy -9585 -450.28 1110 d17 -6385 -450.28 1071 dummy -9505 -450.28 1111 d16 -6305 -450.28 1072 extc -9425 -450.28 1112 d15 -6225 -450.28 1073 dgndo -9345 -450.28 1113 d14 -6145 -450.28 1074 im0 -9265 -450.28 1114 d13 -6065 -450.28 1075 vddio -9185 -450.28 1115 d12 -5985 -450.28 1076 im1 -9105 -450.28 1116 d11 -5905 -450.28 1077 dgndo -9025 -450.28 1117 d10 -5825 -450.28 1078 im2 -8945 -450.28 1118 d9 -5745 -450.28 1079 vddio -8865 -450.28 1119 d8 -5665 -450.28 1080 p68 -8785 -450.28 1120 dgndo -5585 -450.28
ST7787 v1.7 2008.04.18 18 pad no. pin name x y pad no. pin name x y 1121 dummy -5505 -450.28 1161 dgnd -2380 -450.28 1122 test_en -5425 -450.28 1162 dgnd -2315 -450.28 1123 d7 -5345 -450.28 1163 dgnd -2250 -450.28 1124 d6 -5265 -450.28 1164 vddi -2170 -450.28 1125 d5 -5185 -450.28 1165 vddi -2105 -450.28 1126 d4 -5105 -450.28 1166 vddi -2040 -450.28 1127 d3 -5025 -450.28 1167 vddi -1975 -450.28 1128 d2 -4945 -450.28 1168 vref -1895 -450.28 1129 d1 -4865 -450.28 1169 vref -1830 -450.28 1130 d0 -4785 -450.28 1170 vref -1765 -450.28 1131 tpo0 -4705 -450.28 1171 regp -1685 -450.28 1132 tpo1 -4625 -450.28 1172 regpt -1605 -450.28 1133 tpo2 -4545 -450.28 1173 vcc -1525 -450.28 1134 tpo3 -4465 -450.28 1174 vcc -1460 -450.28 1135 tpo4 -4385 -450.28 1175 vcc -1395 -450.28 1136 tpo5 -4305 -450.28 1176 vcc -1330 -450.28 1137 tpo6 -4225 -450.28 1177 vcc -1265 -450.28 1138 tpo7 -4145 -450.28 1178 vcc -1200 -450.28 1139 osc -4065 -450.28 1179 dummy -1120 -450.28 1140 te -3985 -450.28 1180 dummy -1040 -450.28 1141 csx -3905 -450.28 1181 vci1 -960 -450.28 1142 rdx -3825 -450.28 1182 vci1 -895 -450.28 1143 wrx -3745 -450.28 1183 vci1 -830 -450.28 1144 sda -3665 -450.28 1184 vci1 -765 -450.28 1145 dummy -3585 -450.28 1185 agnd -685 -450.28 1146 auto -3505 -450.28 1186 agnd -620 -450.28 1147 resx -3425 -450.28 1187 agnd -555 -450.28 1148 dgnd -3345 -450.28 1188 agnd -490 -450.28 1149 d/cx -3265 -450.28 1189 agnd -425 -450.28 1150 dgnd -3185 -450.28 1190 agnd -360 -450.28 1151 pclk -3105 -450.28 1191 agnd -295 -450.28 1152 dgnd -3025 -450.28 1192 agnd -230 -450.28 1153 de -2945 -450.28 1193 vdd -150 -450.28 1154 hs -2865 -450.28 1194 vdd -85 -450.28 1155 vs -2785 -450.28 1195 vdd -20 -450.28 1156 dgnd -2705 -450.28 1196 vdd 45 -450.28 1157 dgnd -2640 -450.28 1197 vdd 110 -450.28 1158 dgnd -2575 -450.28 1198 vdd 175 -450.28 1159 dgnd -2510 -450.28 1199 vdd 240 -450.28 1160 dgnd -2445 -450.28 1200 vdd 305 -450.28
ST7787 v1.7 2008.04.18 19 pad no. pin name x y pad no. pin name x y 1201 vdd 370 -450.28 1241 c12n 3075 -450.28 1202 vdd 435 -450.28 1242 c12n 3140 -450.28 1203 avdd 515 -450.28 1243 c12n 3205 -450.28 1204 avdd 580 -450.28 1244 c12n 3270 -450.28 1205 avdd 645 -450.28 1245 c12n 3335 -450.28 1206 avdd 710 -450.28 1246 dummy 3415 -450.28 1207 avdd 775 -450.28 1247 dummy 3495 -450.28 1208 avdd 840 -450.28 1248 agnd 3575 -450.28 1209 avdd 905 -450.28 1249 agnd 3640 -450.28 1210 avddo 970 -450.28 1250 agnd 3705 -450.28 1211 avddo 1035 -450.28 1251 agnd 3770 -450.28 1212 avdds 1100 -450.28 1252 agnd 3835 -450.28 1213 c1so 1180 -450.28 1253 agnd 3900 -450.28 1214 c1so 1245 -450.28 1254 agnd 3965 -450.28 1215 vc1s 1310 -450.28 1255 agnd 4030 -450.28 1216 vc1s 1375 -450.28 1256 dummy 4110 -450.28 1217 vc1s 1440 -450.28 1257 dummy 4190 -450.28 1218 vc1s 1505 -450.28 1258 vcl 4270 -450.28 1219 gvdd 1585 -450.28 1259 vcl 4335 -450.28 1220 gvdd 1650 -450.28 1260 vcl 4400 -450.28 1221 gvdd 1715 -450.28 1261 vclo 4465 -450.28 1222 c11p 1795 -450.28 1262 vclo 4530 -450.28 1223 c11p 1860 -450.28 1263 vcls 4595 -450.28 1224 c11p 1925 -450.28 1264 c21p 4675 -450.28 1225 c11p 1990 -450.28 1265 c21p 4740 -450.28 1226 c11p 2055 -450.28 1266 c21p 4805 -450.28 1227 c11p 2120 -450.28 1267 c21p 4870 -450.28 1228 c11n 2200 -450.28 1268 c21n 4950 -450.28 1229 c11n 2265 -450.28 1269 c21n 5015 -450.28 1230 c11n 2330 -450.28 1270 c21n 5080 -450.28 1231 c11n 2395 -450.28 1271 c21n 5145 -450.28 1232 c11n 2460 -450.28 1272 c22p 5225 -450.28 1233 c11n 2525 -450.28 1273 c22p 5290 -450.28 1234 c12p 2605 -450.28 1274 c22p 5355 -450.28 1235 c12p 2670 -450.28 1275 c22p 5420 -450.28 1236 c12p 2735 -450.28 1276 c22n 5500 -450.28 1237 c12p 2800 -450.28 1277 c22n 5565 -450.28 1238 c12p 2865 -450.28 1278 c22n 5630 -450.28 1239 c12p 2930 -450.28 1279 c22n 5695 -450.28 1240 c12n 3010 -450.28 1280 c23p 5775 -450.28
ST7787 v1.7 2008.04.18 20 pad no. pin name x y pad no. pin name x y 1281 c23p 5840 -450.28 1321 vcom 8620 -450.28 1282 c23p 5905 -450.28 1322 vcom 8685 -450.28 1283 c23p 5970 -450.28 1323 vcom 8750 -450.28 1284 c23n 6050 -450.28 1324 vcom 8815 -450.28 1285 c23n 6115 -450.28 1325 vcom 8880 -450.28 1286 c23n 6180 -450.28 1326 vcom 8945 -450.28 1287 c23n 6245 -450.28 1327 vcom 9010 -450.28 1288 dummy 6325 -450.28 1328 dummy 9090 -450.28 1289 dummy 6405 -450.28 1329 dummy 9170 -450.28 1290 vgl 6485 -450.28 1330 vpp 9250 -450.28 1291 vgl 6550 -450.28 1331 vpp 9315 -450.28 1292 vgl 6615 -450.28 1332 vpp 9380 -450.28 1293 vgl 6680 -450.28 1333 vpp 9445 -450.28 1294 vgls 6745 -450.28 1334 dummy 9525 -450.28 1295 dummy 6825 -450.28 1335 dummy 9605 -450.28 1296 dummy 6905 -450.28 1297 vgh 6985 -450.28 1298 vgh 7050 -450.28 1299 vgho 7115 -450.28 1300 vgho 7180 -450.28 1301 vghs 7245 -450.28 1302 dummy 7325 -450.28 1303 dummy 7405 -450.28 1304 vcomh 7485 -450.28 1305 vcomh 7550 -450.28 1306 vcomh 7615 -450.28 1307 vcomh 7680 -450.28 1308 vcomh 7745 -450.28 1309 vcomh 7810 -450.28 1310 vcomh 7875 -450.28 1311 vcomh 7940 -450.28 1312 vcoml 8020 -450.28 1313 vcoml 8085 -450.28 1314 vcoml 8150 -450.28 1315 vcoml 8215 -450.28 1316 vcoml 8280 -450.28 1317 vcoml 8345 -450.28 1318 vcoml 8410 -450.28 1319 vcoml 8475 -450.28 1320 vcom 8555 -450.28
ST7787 v1.7 2008.04.18 21 5. block diagram 720sourcebuffer dac levelshifter datalatch colorconversion luttable displayram 240x18x320 voltagereference gammacircuit gammatable displaycontrol 320gatebuffer levelshifter gatedecoder vcomgenerator osc booster1/2/4 instruction register mutiple otp rgbi/f mcuif rev rl tb shut pclk de hsync vsync sda lcm[1:0] rcm[1:0] srgb gs wrx rdx csx dc/x(scl) im[2:0] p68 extc smx smy d[17:0] vgl vgh vcl avdd vddi vdd vref gvdd vci1 vcomh vcoml vcom c11p c12p c11n c12n c21n c21p c22p c23p c22n c23n idm
ST7787 v1.7 2008.04.18 22 6. pin description 6.1 power supply pin name i/o description count connect pin vdd i power supply for analog, digital system and boo ster circuit 10 vdd vddi i power supply for i/o system 4 vddi vpp i power supply for otp circuit 4 vpp agnd i system ground for analog system and booster ci rcuit 16 gnd dgnd i system ground for i/o system and internal dig ital system 11 gnd 6.2 interface logic pin name i/o description count connect pin p68 i -8080/6800 mcu interface mode select -p68=1, select 6800 mcu parallel interface -p68=0, select 8080 mcu parallel interface -if not used, please fix this pin at vddi or dgnd le vel 1 gnd/vddi im0~im2 i -selection for mcu parallel interface or serial inte rface -if not used, please connect this pin to vddi or dgn d im2 mcu & spi interface mode selection 0 spi interface 1 mcu parallel interface 3 gnd/vddi resx i -this signal will reset the device and it must be a pplied to properly initialize the chip -signal is active low 1 mcu csx i -chip select input pin (low is enable) -this pin can be permanently fixed low in mcu int erface mode only 1 mcu d/cx (scl) i -display data/command selection pin in mcu interfac e -d/cx=1: display data -d/cx=0: command data -in serial interface, this is used as scl -if not used, please connect this pin to vddi or dgn d 1 mcu rdx (e) i -read enable in 8080 mcu parallel interface -read/write operation enable pin in 6800 mcu parall el interface -if not used, please connect this pin to vddi or dg nd 1 mcu wrx i -write enable in mcu parallel interface - read/write operation enable pin in 8080 mcu paral lel interface -if not used, please connect this pin to vddi or dg nd - in rgb interface, wrx are not used and should be co nnected to vddi 1 mcu sda i -when rcm1, rcm0=1x (rgb interface), this pin is used as serial input/output pin. -when rcm1, rcm0=0x (mcu interface), this pin is not used and please connect to vddi or dgnd level. the serial in put/output pin in mcu interface mode is d0. 1 mcu dgnd/vddi osc o -monitoring pin of internal oscillator clock and is turned on/off by s/w command -when this pin is inactive (function off), this pin is dgnd level -if not used, please keep this pin open 1 - d[17:0] i/o -when rcm=1 (rgb interface), d[17:0] are used as rgb interface data bus -when rcm=0 (mcu interface), d[17:0] are used as mcu parallel interface data bus - d0 is the serial input/output signal in serial inte rface mode - in serial interface, d[17:1] are not used and shoul d be connected to vddi or dgnd 18 mcu te i/o -tearing effect output pin to synchronies mcu to fr ame writing, activated by s/w command -external vsync signal input pin with mcu interface . -when this pin is not inactive, this pin is low -if not used, please open this pin 1 mcu pclk i -pixel clock signal in rgb interface mode -if not used, please fix this pin at vddi or dgnd 1 rgb interface vs i -vertical sync. signal in rgb interface mode -if not used, please fix this pin at vddi or dgnd 1 rgb interface hs i -horizontal sync. signal in rgb interface mode -if not used, please fix this pin at vddi or dgnd 1 rgb interface de i -data enable signal in rgb interface mode 1 rg b interface
ST7787 v1.7 2008.04.18 23 -if not used, please fix this pin at vddi or dgnd note1. if csx is connected to ground in parallel inte rface mode, there will be no abnormal visible effec t on the display module. also there will be no restriction on using t he parallel read/write protocols, power on/off sequ ences or other functions. furthermore there will be no influ ence to the power consumption of the display module . note2. when in 8-line parallel mode (im2 , im1, im0 =001) then if some data or signal appears on d[1 7:8] then it will have no influence to the system. (d[17:8] can be co nnected to1 or 0) note3. when csx=1, there is no influence to the par allel and serial interface. note4. 1 = vddi level, 0 = dgnd level.
ST7787 v1.7 2008.04.18 24 6.3 mode selection pin name i/o description count connect pin extc i -to use extended command set, please connect this p in to vddi -during normal operation, please open this pin (int ernal r pull-down =2m ) extc enable/disable modification of extend command 0 only use default command set 1 use extended command table (command register can be modify by user) 1 vddi/gnd gs i -gamma arrangement selection pin when lcm[1]=0,lcm[ 0]=0 gs gc[7:0] reg. lcm1 lcm0 lc type gamma 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 01h 1 1 n/a curve 2.2 02h x x transflective(tr) 1.8 04h x x transflective(tr) 2.5 1 08h x x transflective(tr) 1.0 01h x x transflective(tr) 1.0 02h x x transflective(tr) 2.5 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 04h 1 1 n/a curve 2.2 0 08h x x transflective(tr) 1.8 1 vddi/gnd idm i -normal mode and idle mode selection pin -please refer rgb interface for detail usage idm enable/disable idle mode 0 normal display (can be changed to idle mode by s/ w) 1 idle mode enable 1 vddi/gnd lcm1, lcm0 i -liquid crystal (lc) type selection pins lcm[1:0] selection of lc type 0 0 mva 0 1 transflective 1 0 transmissive 1 1 reserved 1 vddi/gnd rcm1, rcm0 i -rgb or mcu interface mode selection pins rcm[1:0] selection of mcu or rgb interface 00 0 mcu interface 01 1 mcu interface 10 2 rgb interface (1) 11 3 rgb interface (2) 2 vddi/gnd srgb i -rgb arrangement selection pin for color filter des ign srgb rgb arrangement 0 s1, s2, s3 filter order = r , g , b 1 s1, s2, s3 filter order = b , g , r -please refer chapter 14 for detail using 1 vddi/gnd smx i -scanning direction of source output selection pin smx scanning direction of source output 0 s1 -> s720 1 s720 -> s1 -please refer chapter 14 for detail using 1 vddi/gnd smy i -scanning direction of gate output selection pin smy scanning direction of gate output 0 g1 -> g320 1 vddi/gnd
ST7787 v1.7 2008.04.18 25 1 g320 -> g1 -please refer chapter 14 for detail using rev i -polarity of source output selection pin rev polarity of source output 0 data not reverse 1 data reverse -please refer rgb interface for detail using -if not used, please fix this pin at vddi or dgnd 1 vddi/gnd shut i -display on/off control pin in rgb interface shut display on/off 0 display on 1 display off -please refer rgb interface for detail using -if not used, please fix this pin at vddi or dgnd 1 vddi/gnd rl i -scanning direction of source output selection pin in rgb interface rl smx scanning direction of source output 0 0 s1 -> s720 0 1 s720 -> s1 1 0 s720 -> s1 1 1 s1 -> s720 -please refer rgb interface for detail using -if not used, please fix this pin at vddi or dgnd l evel 1 vddi/gnd tb i -scanning direction of gate output selection pin in rgb interface tb smy scanning direction of gate output 0 0 g1 -> g320 0 1 g320 -> g1 1 0 g320 -> g1 1 1 g1 -> g320 -please refer rgb interface for detail using -if not used, please fix this pin at vddi or dgnd 1 vddi/gnd auto i -enable/disable the automatic power-on sequence auto automatic power-on sequence enable/disable 0 reserved 1 enable (auto mode) 1 vddi test_en i -enable/disable the test mode test_en test mode enable/disable 0 disable 1 enable 1 vddi/gnd 6.4 driver output pin name i/o description count connect pin s1 to s720 o -source driver output pins 720 - g1 to g320 o -gate driver output pins 320 - vci1 i/o -a reference voltage for step-up circuit 1 -connect a capacitor for stabilization. 4 capacitor avdd i -power input pin for analog circuit block -in normal usage, connect it to avdd 7 capacitor avddo o -a power output pin that the voltage is generated f rom power block -output of booster 1 circuit -connect a capacitor for stabilization. 2 avdd avdds i - a reference voltage for step-up circuit 2 1 avd d vc1s i - a reference voltage for analog circuit including gamma, source and gate 4 capacitor c1so o - output of regulator in 2x boost system 2 c 1s vcl i -power input pin for vcom circuit -in normal usage, connect it to vcl 3 capacitor vclo o -a power output pin of step-up circuit 4 -when vcoml is higher than agnd, vcl=agnd -connect a capacitor for stabilization 2 vcl vcls i - a reference voltage for step-up circuit 2 1 vcl vgh i -power input pin for gate driver circuit -in normal usage, connect it to vgh 2 vgh vgho o -positive output pin of the step-up circuit 2 2 capacitor
ST7787 v1.7 2008.04.18 26 -connect a capacitor for stabilization vghs i - a reference voltage for step-up circuit 2 1 vgh vgl i -power input pin for gate driver circuit -in normal usage, connect it to vgl 2 capacitor vglo o -negative output of the step-up circuit 2 -connect a capacitor for stabilization 2 vgl vgls i - a reference voltage for step-up circuit 2 1 vgl vref o -reference voltage for power circuit block. -connect a capacitor for stabilization 3 capacitor gvdd o -a standard level for grayscale voltage generator -connect a capacitor for stabilization. -when internal gvdd generator is not used, connect an external power supply (avdd-0.5v) 3 capacitor vcomh o -positive voltage output of vcom -connect a capacitor for stabilization 8 capacitor vcoml o -negative voltage output of vcom -connect a capacitor for stabilization 8 capacitor vcom o -a power supply for the tft-lcd common electrode 8 common electrode c11p, c11n c12p, c12n o -capacitor connecting pins for step-up circuit 1 (for avdd) 24 step-up capacitor c21p, c21n c22p, c22n c23p, c23n o -capacitor connecting pins for step-up circuit 2 (for vgh, vgl, vcl) 24 step-up capacitor vddio o -vddi voltage output level for monitoring 8 - dgndo o -dgnd voltage output level for monitoring 9 - vcc o -monitoring pin of internal digital reference volta ge -connect a capacitor fir stabilization 6 capacitor regp regpt o test pin 2 open 6.5 test pin name i/o description count connect pin tpi, tpo i/o -test pins. in regular usage, please open these pins 12 open dummy -these pins are dummy (have no function inside) -can allow signal traces pass through under these p ads on tft glass 24 open
ST7787 v1.7 2008.04.18 27 7. driver electrical characteristics 7.1 absolute operation range item symbol rating unit supply voltage vdd - 0.3 ~ +4.6 v supply voltage (logic) vddi - 0.3 ~ +4.6 v supply voltage (digital) vcc -0.3 ~ +4.6 v driver supply voltage vgh-vgl -0.3 ~ +30.0 v logic input voltage range v in 0.5 ~ vddi + 0.5 v logic output voltage range v o 0.5 ~ vddi + 0.5 v operating temperature range t opr -30 ~ +70 storage temperature range t stg -55 ~ +125 note: if one of the above items is exceeded its max imum limitation momentarily, the quality of the pro duct may be degraded. absolute maximum limitation, therefore, sp ecify the values exceeding which the product may be physically damaged. be sure to use the product withi n the recommend range. 7.2 esd protection level model test condition protection level unit human body model c = 100 pf, r = 1.5k ohm. 3 times zapping/each pin, 1sec/per zapping 2500 for each pin 3000 for connecter pin v machine model c = 200 pf, r = 0.0 ohm. 3 times zapping/each pin, 1sec/per zapping 250 for each pin v note: connecter pin is data bus, power, csx, rdx, wrx, resx, te. 7.3 latch-up protection level the device will not latch up at trigger current lev el less than 100 ma. 7.4 light sensitivity the operation of the ic will not be materially alte red by incident light. 7.5 dc characteristic specification parameter symbol condition min typ max unit related pins power & operation voltage system voltage vdd operating voltage 2.45 2.78 3.3 v note 2 interface operation voltage vddi i/o supply voltage 1.65 1.8/2.78 3.3 v note 2 digital operating voltage vcc digital supply voltage 1.65 2.0 v note 2 gate driver high voltage vgh 10 16.5 v note 3 gate driver low voltage vgl -14 -5 v note 3 gate driver supply voltage | vgh-vgl | 19 30 v note 3 i/o operating voltage 1.65 3.3 v otp operation voltage vpp operating voltage 7.5 7.8 v input / output logic-high input voltage v ih 0.7vddi vddi v note 1,2,3 logic-low input voltage v il vss 0.3vddi v note 1,2,3 logic-high output voltage v oh i oh = -1.0ma 0.8vddi vddi v note 1,2,3 logic-low output voltage v ol i ol = +1.0ma vss 0.2vddi v note 1,2,3 logic-high input current i ih vin = vddi or vss 1 ua note 1,2,3 logic-low input current i il -1 ua note 1,2,3 input leakage current i il ioh = -1.0ma -0.1 +0.1 ua note 1,2,3 vcom voltage vcom high voltage vcomh ccom=12nf 2.5 5.0 v note 3 vcom low voltage vcoml ccom=12nf -2.5 0.0 v note 3 vcom amplitude vcomac |vcomh-vcoml| 4.0 6.0 v note 3 source driver source output range vsout 0.1 avdd-0.1 v note 4 gamma reference voltage gvdd 3.0 5.0 v note 3 source output settling time tr below with 99% precision 10 14 us note 4,5 sout >=4.2v, sout<=0.8v 20 mv note 4,5 output deviation voltage (source output channel) vdev 4.2v>sout>0.8v 15 mv
ST7787 v1.7 2008.04.18 28 output offset voltage v ofset 35 mv note 6 step-up circuit internal reference voltage v ref % note 3 1st step-up (vddx2) voltage avdd 4.95 6.0 v note 3 1st step-up (vddx2) drop voltage vddx2,dorp i avdd = 2.5ma (include panel loading) 4% % note 3 linear range v linear 0.2 avdd-0.2 v note 1: vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgn d=0v, ta=-30 to 70 note 2, 3, 4: when the measurements are performed w ith lcd module, measured points are like below. note 3: p68, csx, rdx, wrx, d[17:0], d/cx, resx, te, pclk, vs, hs, extc, gs, idm, scl, lcm[1:0], rcm[1:0], im[2:0], srgb, smx, smy, rev, shut, rl, tb and test pins note 5, source channel loading= 2.2kohm , 10pf/chan nel, gate channel loading=0.8kohm , 50pf/channel. note 6, the max. value is between measured point of note 4 and gamma setting value. fig. 7.5.1 example of measured point on the panel fig. 7.5.2 tr: the source output stabling time. fig. 7.5.3 source output deviation (channel to chan nel). -when sout >=4.2v, sout<=0.8v max (s1, s2, s3, . , s720) C min (s1, s2, s3, . , s720) <= 20mv -when 4.2v>sout>0.8v max (s1, s2, s3, . , s720) C min (s1, s2, s3, . , s720) <= 6mv -example when sout level is 3.95v (gray scale voltage) max (s1, s2, s3, . , s720) = 3.96v min (s1, s2, s3, , s720) = 3.944v sout deviation =max (s1, s2, s3, . , s720) C min ( s1, s2, s3, . , s720) = 10mv <- out of spec
ST7787 v1.7 2008.04.18 29 7.6 power consumption current consumption typical maximum operation mode inversion mode image iddi (ua) idd (ma) iddi (ua) idd (ma) one line note 1 1 2.6 1 3.0 -normal mode one line note 2 1 2.5 1 2.8 -partial + idle mode (40 lines) one line note 3,4 1 0.65 1 0.8 -sleep-in mode n/a n/a 1 9ua 1 9ua notes: 1. all pixels black. 2. grayscale from top to bottom. 3. black & white checker board 8 by 8 4. absolute worst case patterns: all pixels black. typical case: ta = 25 vdd = 2.78 v vddi = 1.80 v worst case: ta = -30 to 70 vdd = 2.45 v to 3.3 v vddi = 1.65 v to 3.3 v includes process variance.
ST7787 v1.7 2008.04.18 30 8. timing chart 8.1 parallel interface characteristics: 18, 16, 9 o r 8-bits bus (8080-series mcu interface) fig. 8.1.1 parallel interface timing characteristic s (8080-series mcu interface) signal symbol parameter min max unit description t ast address setup time 10 - ns d/cx t aht address hold time (write/read) 10 - ns - t chw chip select h pulse width 0 - ns t cs chip select setup time (write) 15 - ns t rcs chip select setup time (read id) 45 - ns t rcsfm chip select setup time (read ram) 355 - ns t csf chip select wait time (write/read) 10 - ns csx t csh chip select hold time 10 - ns -(3-transfer for one pixel) t wc write cycle 66 - ns t wrh control pulse h duration 20 - ns wrx t wrl control pulse l duration 20 - ns -(15mhz) t rc read cycle (id) 160 - ns t rdh control pulse h duration (id) 90 - ns rdx (id) t rdl control pulse l duration (id) 45 - ns when read id data t rcfm read cycle (fm) 450 - ns t rdhfm control pulse h duration (ram) 90 - ns rdx (fm) t rdlfm control pulse l duration (ram) 355 - ns when read from frame memory t dst data setup time 20 - ns t dht data hold time 20 - ns t rat read access time (id) - 40 ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 20 80 ns for maximum cl=30pf for minimum cl=8pf note 1: vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgn d=0v, ta=-30 to 70
ST7787 v1.7 2008.04.18 31 fig. 8.1.2 rising and falling timing for input and output signal fig.8.1.3 chip selection (csx) timing fig. 8.1.4 write-to-read and read-to-write timing note: the rising time and falling time (tr, tf) of i nput signal and fall time are specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vddi for input signals.
ST7787 v1.7 2008.04.18 32 8.2 parallel interface characteristics: 18, 16, 9 o r 8-bits bus (6800-series mcu interface) csx d/cx d[17:0] write d[17:0] read v ih v il v ih v il t chw t chw t csh t csf t ast t rcs /t rcsfm /wx e rx e t cs v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t aht t wc t wrh t wrl t dst t dht t rdh /t rdhfm t rdl /t rdlfm t rc /t rcfm t rat /t ratfm t odh fig. 8.2.1 parallel interface timing characteristic s (6800-series mcu interface) signal symbol parameter min max unit description t ast address setup time 10 - ns d/cx t aht address hold time (write/read) 10 - ns - t chw chip select h pulse width 0 - ns t cs chip select setup time (write) 15 - ns t rcs chip select setup time (read id) 45 - ns t rcsfm chip select setup time (read fm) 355 - ns t csf chip select wait time (write/read) 10 - ns csx t csh chip select hold time 10 - ns - t wc write cycle 66 - ns t wrh control pulse h duration 20 - ns wrx t wrl control pulse l duration 20 - ns -(15mhz) t rc read cycle (id) 160 - ns t rdh control pulse h duration (id) 90 - ns rdx (id) t rdl control pulse l duration (id) 45 - ns when read id data t rcfm read cycle (fm) 450 - ns t rdhfm control pulse h duration (fm) 90 - ns rdx (fm) t rdlfm control pulse l duration (fm) 355 - ns when read from frame memory t dst data setup time 20 - ns t dht data hold time 20 - ns t rat read access time (id) - 40 ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 20 80 ns for maximum cl=30pf for minimum cl=8pf note 1: vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgn d=0v, ta=-30 to 70 note 2: the rising time and falling time (tr, tf) o f input signal and fall time are specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vddi for input signals.
ST7787 v1.7 2008.04.18 33 8.3 serial interface characteristics (3-line serial ) csx v ih v il t chw t csh t oh t css scl sda sda (dout) t scc t scycw /t scycr t acc v ih v il v ih v il v ih v il v ih v il t sds t sdh t shw /t shr t slw /t slr fig. 8.3.1 3-line serial interface timing signal symbol parameter min max unit description t css chip select setup time 60 ns t csh chip select hold time 60 ns t scc chip select setup time 20 ns csx t chw chip select setup time 40 ns t scycw serial clock cycle (write) 66 ns t shw scl h pulse width (write) 20 ns t slw scl l pulse width (write) 20 ns t scycr serial clock cycle (read) 150 ns t shr scl h pulse width (read) 60 ns scl t slr scl l pulse width (read) 60 ns t sds data setup time 10 ns t sdh data hold time 10 ns t acc access time 10 ns sda (din) (dout) t oh output disable time 15 ns for maximum cl=30pf for minimum cl=8pf table 8.3: 3-line serial interface characteristics note 1: vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgn d=0v, ta=-30 to 70 note 2: the rising time and falling time (tr, tf) o f input signal and fall time are specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vddi for input signals. 8.4 vertical synchronizing signal timing characteri stic fig. 8.4 vertical synchronizing signal timing signal symbol parameter min max unit description tvcyc vsync cycle 1f+2h - - tvlw vsync pulse l width 1h 1f-1h - vsync tvhw vsync pulse h width 3h - -standing up standing fall time of the input signal (tr,tf) is provided for by 15ns or less. -the signal level is provided for based on 30% and 70% of vddi-dgnd -this is provided for while external vsync is synch ronizing. -f indicates the time of one frame in internal sync hronizition. -h indicates the time in internal synchronizition f or one line.
ST7787 v1.7 2008.04.18 34 9. function description 9.1 interface type selection the selection of given interfaces are done by setti ng p68, im2, im1, and im0 pins as shown in followin g table. p68 im2 im1 im0 interface read back selection - 0 - - 3-line serial interface via the read instru ction 0 1 0 0 8080 8-bit parallel rdx strobe (8-bit read data and 8-bit read parameter) 0 1 0 1 8080 16-bit parallel rdx strobe (16-bit rea d data and 8-bit read parameter) 0 1 1 0 8080 9-bit parallel rdx strobe (9-bit read data and 8-bit read parameter) 0 1 1 1 8080 18-bit parallel rdx strobe (18-bit rea d data and 8-bit read parameter) - 0 - - 3-line serial interface via the read instru ction 1 1 0 0 6800 8-bit parallel e strobe (8-bit read da ta and 8-bit read parameter) 1 1 0 1 6800 16-bit parallel e strobe (16-bit read data and 8-bit read parameter) 1 1 1 0 6800 9-bit parallel e strobe (9-bit read da ta and 8-bit read parameter) 1 1 1 1 6800 18-bit parallel e strobe (18-bit read data and 8-bit read parameter) p68 im2 im1 im0 interface rdx wrx d/cx read back selection - 0 - - 3-line serial interface note1 note1 scl d[17:1]: unused, d0: sda 0 1 0 0 8080 8-bit parallel rdx wrx d/cx d[17:8]: unused, d7-d0: 8-bit data 0 1 0 1 8080 16-bit parallel rdx wrx d/cx d[17:16]: unused, d15-d0: 16-bit data 0 1 1 0 8080 9-bit parallel rdx wrx d/cx d[17:9]: unused, d8-d0: 9-bit data 0 1 1 1 8080 18-bit parallel rdx wrx d/cx d17-d0: 18-bit data 1 1 0 0 6800 8-bit parallel e wrx rs d[17:8]: unused, d7-d0: 8-bit data 1 1 0 1 6800 16-bit parallel e wrx rs d[17:16]: unused, d15-d0: 16-bit data 1 1 1 0 6800 9-bit parallel e wrx rs d[17:9]: unused, d8-d0: 9-bit data 1 1 1 1 6800 18-bit parallel e wrx rs d17-d0: 18-bit data note 1. unused pins can be open, or connected to dg nd or vddi. 9.2 8080-series mcu parallel interface (p68=0) the mcu can use on of following interfaces: 11-line s with 8-data parallel interface, 12-lines with 9-d ata parallel interface, 19-lines with 16-data parallel interface or 21-line s with 18-data parallel interface. the chip-select csx (active low) enables/disables the parallel interface. resx (acti ve low) is an external reset signal. wrx is the par allel data write, rdx is the parallel data read and d[17:0] is parallel d ata. the graphics controller chip reads the data at the rising edge of wrx signal. the d/cx is the data/com mand flag. when d/cx=1, d[17:0] bits are either display data or c ommand parameters. when d/c=0, d[17:0] bits are c ommands. the 6800-series bi-directional interface can be use d for communication between the micro controller an d lcd driver chip. the selection of this interface is done when p68 pi n is in low state (dgnd). interface bus width can b e selected with im2, im1 and im0. the interface functions of 8080-series parallel int erface are given in following table. p68 im2 im1 im0 interface rdx wrx d/cx read back selection 0 1 write 8-bit command (d7 to d0) 1 1 write 8-bit display data or 8-bit parameter (d7 to d0) 1 1 read 8-bit display data (d7 to d0) 0 1 0 0 8-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 write 16-bit display data or 8-bit parameter (d15 to d0) 1 1 read 16-bit display data (d15 to d0) 0 1 0 1 16-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 write 9-bit display data or 8-bit parameter (d8 to d0) 1 1 read 9-bit display data (d8 to d0) 0 1 1 0 9-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 write 18-bit display data or 8-bit parameter (d17 to d0) 1 1 read 18-bit display data (d17 to d0) 0 1 1 1 18-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) note: applied for command code: dah, dbh, dch, 04h, 0 9h, 0ah, 0bh, 0ch, 0dh, 0eh, 0fh
ST7787 v1.7 2008.04.18 35 9.2.1 write cycle sequence fig. 9.2.1 8080-series wrx protocol note: wrx is an unsynchronized signal (it can be sto pped). fig. 9.2.2 8080-series parallel bus protocol, write to register or display ram
ST7787 v1.7 2008.04.18 36 9.2.2 read cycle sequence the read cycle (rdx high-low-high sequence) means t hat the host reads information from display via int erface. the driver sends data (d[17:0]) to the host when there is a falling edge of rdx and the host reads data wh en there is a rising edge of rdx. fig. 9.2.3 8080-series rdx protocol note: rdx is an unsynchronized signal (it can be sto pped). cmd dm pa cmd dm&data data data s p cmd dm pa cmd dm&data data data s p d[17:0] resx csx d/cx rdx wrx d[17:0] hostd[17:0] hosttolcd driverd[17:0] lcdtohost ? 1 ? hiz readparameter readdisplaydata cmd:writecommandcode pa:parameterordisplaydata signalsond[17:0],d/cx,r/wx,e pinsduringcsx=1areignored. dm pa1 dm&data pa n2 pa n1 p s cmd cmd s p hiz hiz hiz fig. 9.2.4 8080-series parallel bus protocol, read data from register or display ram
ST7787 v1.7 2008.04.18 37 9.3 6800-series parallel interface (p68=1) the mcu uses a 11-lines 8-data parallel interface o r 12-lines 9-data parallel interface or 19-lines 16 -data parallel interface or 21-lines 18-data parallel interface. the chip-se lect csx(active low) enables and disables the paral lel interface. resx (active low) is an external reset signal. the r/wx is the read/write flag and d[17:0] is parallel data . the graphics controller chip reads the data at the falling edge of e signal when r/wx= 1 and writes the data at the falling of the e signal when r/wx=0. the d/cx is the data /command flag. when d/cx=1, d[17:0] bits are disp lay ram data or command parameters. when d/c= 0, d[17:0] bits are commands. the 6800-series bi-directional interface can be use d for communication between the micro controller an d lcd driver chip. the selection of this interface is done when p68 pi n is high state (vddi). interface bus width can be selected with im2, im1 and im0. the interface functions of 6800-series parallel int erface are given in table 9.3.1. table 9.3.1 the function of 6800-series parallel in terface p68 im2 im1 im0 interface d/cx r/wx e function 0 0 write 8-bit command (d7 to d0) 1 0 write 8-bit display data or 8-bit parameter (d7 to d0) 1 1 read 8-bit display data (d7 to d0) 1 1 0 0 8-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 0 write 16-bit display data or 8-bit parameter (d15 to d0) 1 1 read 16-bit display data (d15 to d0) 1 1 0 1 16-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 0 write 9-bit display data or 8-bit parameter (d8 to d0) 1 1 read 9-bit display data (d8 to d0) 1 1 1 0 9-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 0 write 18-bit display data or 8-bit parameter (d17 to d0) 1 1 read 18-bit display data (d17 to d0) 1 1 1 1 18-bit parallel 1 1 read 8-bit parameter or status (d7 to d0) note: applied for command code: dah, dbh, dch, 04h, 0 9h, 0ah, 0bh, 0ch, 0dh, 0eh, 0fh. 9.3.1 write cycle sequence the write cycle means that the host writes informat ion (command or/and data) to the display via the in terface. each write cycle (e low-high-low sequence) consists of 3 contr ol (d/cx, e, r/wx) and data signals (d[17:0]). d/cx bit is a control signal, which tells if the data is a command or a d ata. the data signals are the command if the contro l signal is low (=0) and vice versa it is data (=1). fig. 9.3.1 6800-series write protocol note: e is an unsynchronized signal (it can be stopp ed)
ST7787 v1.7 2008.04.18 34 fig. 9.3.2 6800-series parallel bus protocol, write to register or display ram 9.3.2 read cycle sequence the write cycle means that the host reads informati on (command or/and data) to the display via the int erface. each read cycle (e low-high-low sequence) consists of 3 contr ol (d/cx, e, r/wx) and data signals (d[17:0]). d/cx bit is a control signal, which tells if the data is a command or a d ata. the data signals are the command if the contro l signal is low (=0) and vice versa it is data (=1). fig. 9.3.3 6800-series read protocol note: e is an unsynchronized signal (it can be stopp ed)
ST7787 v1.7 2008.04.18 35 cmd dm pa cmd dm&data data data s p cmd dm pa cmd dm&data data data s p d[17:0] resx csx d/cx r/wx e d[17:0] hostd[17:0] hosttolcd driverd[17:0] lcdtohost ? 1 ? hiz readparameter readdisplaydata cmd:writecommandcode pa:parameterordisplaydata signalsond[17:0],d/cx,r/wx,e pinsduringcsx=1areignored. dm pa1 dm&data pa n2 pa n1 p s cmd cmd s p hiz hiz hiz fig. 9.3.4 6800-series parallel bus protocol, read data form register or display ram
ST7787 v1.7 2008.04.18 36 9.4 serial interface the selection of this interface is done by im2. see the table 9.4.1. table 9.4.1 serial interface type selection p68 im2 im1 im0 interface read back selection - 0 - - 3-line serial interface via the read instruction (8-bit, 24-bit and 32-bit read parameter) the serial interface is a 3-lines/ 9-bits bi-direct ional interface for communication between the micro controller and the lcd driver chip. the 3-lines serial use: csx (chip enab le), scl (serial clock) and sda (serial data input/ output) serial clock (scl) is used for interface with mcu only, so it ca n be stopped when no communication is necessary. 9.4.1 command write mode the write mode of the interface means the micro con troller writes commands and data to the lcd driver. 3-lines serial data packet contains a control bit d/cx and a transmissi on byte is transfrerred by the d/cx pin. if d/cx i s low, the transmission byte is interpreted as a command byte. if d/cx is high, the transmission byte is stored in the display data ram (memory write command), or command register as parameter. any instruction can be sent in any order to the dri ver. the msb is transmitted first. the serial inter face is initialized when csx is high. in this state, scl clock pulse or sda data have no effect. a falling edge on csx enables the serial interface and indicates the start of data transmission. fig. 9.4.1 serial interface data stream format when csx is high, scl clock is ignored. during th e high time of csx the serial interface is initiali zed. at the falling edge of csx, scl can be high or low (see fig 6.1.1.2). s da is sampled at the rising edge of csx. d/cx indic ates, whether the byte is command code (d/cx=0) or parameter/ram da ta (d/cx=1). it is sampled when first rising edge of scl (3-lines serial interface) . if csx stays low after the last bit of command/data byte, the serial interface exp ects the d/cx bit (3-lines serial interface) at the next rising edge of scl. fig. 9.4.2 3-line serial interface write protocol ( write to register with control bit in transmission) d/cxd7 d6 d5 d4 d3 d2 d1 d0 d/cxd7 d6 d5 d4 d3 d2 d1 d0 d/cxd7 d6 d5 d4 d3 d2 d1 d0 d/cxd7 d6 d5 d4 d3 d2 d1 d0 msb lsb transmission byte (tb) may be a command or a data 3-line serial data stream format tb tb tb
ST7787 v1.7 2008.04.18 37 9.4.2 read functions the read mode of the interface means that the micro controller reads register value from the driver. t o do the micro controller first has to send a command (read id or register command) and then the following byte is tr ansmitted in the opposite direction. after that csx is required to g o to high before a new command is send (see the bel ow figure). the driver samples the sda (input data) at rising edge of scl, but shifts sda (output data) at the falling edge of scl. thus the micro controller is supported to read at the rising edge of scl. after the read status command has been sent, the sd a line must be set to tri-state no later than at th e falling edge of scl of the last bit. 3-line serial protocol (for rdid1/rdid2/rdid3/0ah/0 bh/0ch/0dh/0eh/0fh command: 8-bit read): 3-line serial protocol (for rddid command: 24-bit r ead) 3-line serial protocol (for rddst command: 32-bit r ead) fig. 9.4.4 3-line serial interface read protocol
ST7787 v1.7 2008.04.18 38 9.5 data transfer break and recovery if there is a break in data transmission by resx pu lse, while transferring a command or frame memory d ata or multiple parameter command data, before bit d0 of the byte h as been completed, then driver will reject the prev ious bits and have reset the interface such that it will be ready to receive command data again when the chip select line (csx) is next activated after resx have been high state. see the following example host (mcutodriver) fig. 9.5.1 serial bus protocol, write mode ? interrupted by resx if there is a break in data transmission by csx pul se, while transferring a command or frame memory da ta or multiple parameter command data, before bit d0 of the byte h as been completed, then driver will reject the prev ious bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the c hip select line (csx) is next activated. see the following example host (mcu to driver) fig. 9.5.2 serial bus protocol, write mode ? interrupted by csx if 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-tr ansmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the para meter where the break occurred is rejected. the int erface is ready to receive next byte as shown below. fig.9.5.3 write interrupts recovery (serial interfa ce) if a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stor ed and the other parameter of that command remains previous value.
ST7787 v1.7 2008.04.18 39 fig. 9.5.4 write interrupts recovery (both serial a nd parallel interface )
ST7787 v1.7 2008.04.18 40 9.6 data transfer pause it will be possible when transferring a command, fr ame memory data or multiple parameter data to invok e a pause in the data transmission. if the chip select line is relea sed after a whole byte of a frame memory data or mu ltiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data tr ansmission from the point where it was paused. if the chip sel ect line is released after a whole byte of a comman d has been completed, then the display module will receive eit her the commands parameters (if appropriate) or a new command when the chip select line is next enabled as shown below . this applies to the following 4 conditions: 1) command-pause-command 2) command-pause-parameter 3) parameter-pause-command 4) parameter-pause-parameter 9.6.1 serial interface pause fig. 9.6.1 serial interface pause protocol (pause b y csx) 9.6.2 parallel interface pause fig. 9.6.2 parallel bus pause protocol (paused by c sx)
ST7787 v1.7 2008.04.18 41 9.7 data transfer modes the module has three kinds color modes for transfer ring data to the display ram. these are 12-bit colo r per pixel, 16-bit color per pixel and 18-bit color per pixel. the dat a format is described for each interface. data can be downloaded to the frame memory by 2 methods. 9.7.1 method 1 the image data is sent to the frame memory in succe ssive frame writes, each time the frame memory is f illed, the frame memory pointer is reset to the start point and the next frame is written. 9.7.2 method 2 image data is sent and at the end of each frame mem ory download, a command is sent to stop frame memor y write. then start memory write command is sent, and a new frame is downloaded. note: 1) these apply to all data transfer color modes on both serial and parallel interfaces. 2) the frame memory can contain both odd and even n umber of pixels for both methods. only complete pix el data will be stored in the frame memory.
ST7787 v1.7 2008.04.18 42 9.8 data color coding 9.8.1 8-bit parallel interface (im2, im1, im0=100) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input, - 65k colors, rgb 5,6,5-bit input, . - 262k colors, rgb 6,6,6-bit input, 9.8.1.1 8-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h there are 2 pixels (6 sub-pixels) per 3-bytes. note1. the data order is as follows, msb=d7, lsb=d0 and picture data is msb=bit 3, lsb=bit 0 for red, green and blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 43 9.8.1.2 8-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah=05h there are 1 pixel (3 sub-pixels) per 2-bytes. r1,bit4 g1,bit2 0 r1,bit3 g1,bit1 0 r1,bit2 g1,bit0 1 r1,bit1 b1,bit4 0 r1,bit0 b1,bit3 1 g1,bit5 b1,bit2 1 g1,bit4 b1,bit1 0 g1,bit3 b1,bit0 0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 100 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 lookuptablefor65k colordatamapping(16bitsto18bits) 16bits 16bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r2,bit4 g2,bit2 r2,bit3 g2,bit1 r2,bit2 g2,bit0 r2,bit1 b2,bit4 r2,bit0 b2,bit3 g2,bit5 b2,bit2 g2,bit4 b2,bit1 g2,bit3 b2,bit0 ? 0 ? note1. the data order is ad follows, msb=d7, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for green and msb=bit 4, lsb=bit 0 for red and blue data. note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 44 9.8.1.3 8-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah=06h there are 1 pixel (3 sub-pixels) per 3-bytes. r1,bit4 0 r1,bit3 0 r1,bit2 1 r1,bit1 0 r1,bit0 1 r1,bit5 1 0 0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 100 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory g1,bit4 g1,bit3 g1,bit2 g1,bit1 g1,bit0 g1,bit5 b1,bit4 b1,bit3 b1,bit2 b1,bit1 b1,bit0 b1,bit5 r2,bit4 r2,bit3 r2,bit2 r2,bit1 r2,bit0 r2,bit5 ? 0 ? note1. the data order is ad follows, msb=d7, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for red, green and blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 45 9.8.2 16-bit parallel interface (im2,im1, im0=101) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input - 65k colors, rgb 5,6,5-bit input - 262k colors, rgb 6,6,6-bit input
ST7787 v1.7 2008.04.18 46 9.8.2.1 16-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h there are 1 pixel (3 sub-pixels) per 1 bytes, 12-bi t/pixel. note1. the data order is ad follows, msb=d11, lsb=d0 an d picture data is msb=bit 3, lsb=bit 0 for red, green an d blue data. note 2.1-times transfer (d11 to d0) is used to tran smit 1 pixel data with the 12-bit color depth infor mation. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 47 9.8.2.2 16-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah=05h there are 1 pixel (3 sub-pixels) per 1 bytes, 16-bi t/pixel. note1. the data order is ad follows, msb=d15, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for green, and msb=b it 4, lsb=bit 0 for red and blue data. note 2.1-times transfer (d15 to d0) is used to tran smit 1 pixel data with the 16-bit color depth infor mation. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 48 9.8.2.3 16-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah=06h there are 2 pixel (6 sub-pixels) per 3 bytes, 18-bi t/pixel. note1. the data order is ad follows, msb=d15, lsb=d0 an d picture data is msb=bits 5, lsb=bit 0 for red, green an d blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 49 9.8.3 9-bit parallel interface (im2, im1, im0=110) different display data formats are available for th ree colors depth supported by listed below. - 262k colors, rgb 6,6,6-bit input 9.8.3.1 write 9-bit data for rgb 6-6-6-bit input (2 62k-color) there are 1 pixel (6 sub-pixels) per 3 bytes, 18-bi t/pixel. r1,bit4 0 r1,bit3 0 r1,bit2 1 r1,bit1 0 r1,bit0 1 r1,bit5 1 0 0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 110 ? wrx rdx ? 1 ? r/wx e d7 d6 d5 d4 d3 d2 d1 d0 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory g1,bit4 g1,bit3 g1,bit2 g1,bit1 g1,bit0 b1,bit4 b1,bit3 b1,bit2 b1,bit1 b1,bit0 b1,bit5 r2,bit4 r2,bit3 r2,bit2 r2,bit1 r2,bit0 r2,bit5 ? 0 ? g1,bit5 d8 g2,bit4 g2,bit3 g2,bit5 b2,bit4 b2,bit3 b2,bit2 b2,bit1 b2,bit0 b2,bit5 g2,bit2 g2,bit1 g2,bit0 note1. the data order is ad follows, msb=d8, lsb=d0 and picture data is msb=bit 5, lsb=bit 0 for red, green and blue data. note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 50 9.8.4 18-bit parallel interface (im2, im1, im0=111 ) different display data formats are available for th ree colors depth supported by listed below. - 4k colors, rgb 4,4,4-bit input - 65k colors, rgb 5,6,5-bit input - 262k colors, rgb 6,6,6-bit input.
ST7787 v1.7 2008.04.18 51 9.8.4.1 18-bit data bus for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h there are 1 pixel (3 sub-pixels) per 1 byte, 12-bit /pixel. g1,bit3 g1,bit2 g1,bit1 g1,bit0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 12bits 12bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r1,bit3 0 r1,bit2 0 r1,bit1 1 r1,bit0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 b1,bit3 b1,bit2 b1,bit1 b1,bit0 g2,bit3 g2,bit2 g2,bit1 g2,bit0 r2,bit3 r2,bit2 r2,bit1 r2,bit0 b2,bit3 b2,bit2 b2,bit1 b2,bit0 g3,bit3 g3,bit2 g3,bit1 g3,bit0 r3,bit3 r3,bit2 r3,bit1 r3,bit0 b3,bit3 b3,bit2 b3,bit1 b3,bit0 g4,bit3 g4,bit2 g4,bit1 g4,bit0 r4,bit3 r4,bit2 r4,bit1 r4,bit0 b4,bit3 b4,bit2 b4,bit1 b4,bit0 pixeln+2 pixeln+3 lookuptablefor4096colordatamapping(12 bitsto18bits) ? 0 ? d17 d16 note1. the data order is ad follows, msb=d11, lsb=d0 an d picture data is msb=bit 3, lsb=bit 0 for red, green an d blue data. note 2.1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 52 9.8.4.2 18-bit data bus for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors , 3ah=05h there are 1 pixel (3 sub-pixels) per 1 byte, 16-bit /pixel. g1,bit3 g1,bit2 g1,bit1 g1,bit0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 16bits 16bits r1 g1 b1 r2 g2 b2 r3 g3 b3 18bits framememory r1,bit3 0 r1,bit2 0 r1,bit1 1 r1,bit0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 b1,bit3 b1,bit2 b1,bit1 b1,bit0 g2,bit3 g2,bit2 g2,bit1 g2,bit0 r2,bit3 r2,bit2 r2,bit1 r2,bit0 b2,bit3 b2,bit2 b2,bit1 b2,bit0 g3,bit3 g3,bit2 g3,bit1 g3,bit0 r3,bit3 r3,bit2 r3,bit1 r3,bit0 b3,bit3 b3,bit2 b3,bit1 b3,bit0 g4,bit3 g4,bit2 g4,bit1 g4,bit0 r4,bit3 r4,bit2 r4,bit1 r4,bit0 b4,bit3 b4,bit2 b4,bit1 b4,bit0 pixeln+2 pixeln+3 lookuptablefor65k colordatamapping(16bitsto18bits) ? 0 ? d17 d16 r1,bit4 r2,bit4 r3,bit4 r4,bit4 g1,bit5 g1,bit4 g2,bit5 g2,bit4 g3,bit5 g3,bit4 g4,bit5 g4,bit4 b1,bit4 b2,bit4 b3,bit4 b4,bit4 note1. the data order is as follows, msb=d15, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for green, and msb=b it 4, lsb=bit 0 for red and blue data. note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 53 9.8.4.3 18-bit data bus for 18-bit/pixel (rgb 6-6-6-bit input), 262k-color s, 3ah=06h there are 1 pixel (3 sub-pixels) per 1 bytes, 18-bi t/pixel. g1,bit3 g1,bit2 g1,bit1 g1,bit0 8080seriescontrolpins 6800seriescontrolpins resx im[2:0] csx d/cx ? 1 ? ? 111 ? wrx rdx ? 1 ? r/wx e d15 d14 d13 d12 d11 d10 d9 d8 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory r1,bit3 0 r1,bit2 0 r1,bit1 1 r1,bit0 0 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 b1,bit3 b1,bit2 b1,bit1 b1,bit0 g2,bit3 g2,bit2 g2,bit1 g2,bit0 r2,bit3 r2,bit2 r2,bit1 r2,bit0 b2,bit3 b2,bit2 b2,bit1 b2,bit0 g3,bit3 g3,bit2 g3,bit1 g3,bit0 r3,bit3 r3,bit2 r3,bit1 r3,bit0 b3,bit3 b3,bit2 b3,bit1 b3,bit0 g4,bit3 g4,bit2 g4,bit1 g4,bit0 r4,bit3 r4,bit2 r4,bit1 r4,bit0 b4,bit3 b4,bit2 b4,bit1 b4,bit0 pixeln+2 pixeln+3 ? 0 ? d17 d16 r1,bit4 r2,bit4 r3,bit4 r4,bit4 g1,bit5 g1,bit4 g2,bit5 g2,bit4 g3,bit5 g3,bit4 g4,bit5 g4,bit4 b1,bit4 b2,bit4 b3,bit4 b4,bit4 r1,bit5 r2,bit5 r3,bit5 r4,bit5 b1,bit5 b2,bit5 b3,bit5 b4,bit5 note1. the data order is ad follows, msb=d17, lsb=d0 an d picture data is msb=bit 5, lsb=bit 0 for read, green a nd blue data. note 2.1-times transfer (d17o d0) is used to transm it 1 pixel data with the 18-bit color depth informa tion. note 3. - = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 54 9.8.5 3-line serial interface different display data formats are available for th ree colors depth supported by the lcm listed below. 4k colors, rgb 4-4-4-bit input 65k colors, rgb 5-6-5-bit input 262k colors, rgb 6-6-6-bit input 9.8.5.1 write data for 12-bit/pixel (rgb 4-4-4-bit input), 4k-colors, 3ah=03h note 1. pixel data with the 12-bit color depth info rmation note 2. the most significant bits are: rx3, gx3 and bx3 note 3. the least significant bits are: rx0, gx0 an d bx0 note 4. x = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 55 9.8.5.2 write data for 16-bit/pixel (rgb 5-6-5-bit input), 65k-colors, 3ah=05h note 1. pixel data with the 16-bit color depth info rmation note 2. the most significant bits are: rx4, gx5 and bx4 note 3. the least significant bits are: rx0, gx0 an d bx0 note 4. x = don't care - can be set to '0' or '1' 9.8.5.3 write data for 18-bit/pixel (rgb 6-6-6-bit input), 262k-colors, 3ah=06h note 1. pixel data with the 18-bit color depth info rmation note 2. the most significant bits are: rx5, gx5 and bx5 note 3. the least significant bits are: rx0, gx0 an d bx0 note 4. x = don't care - can be set to '0' or '1'
ST7787 v1.7 2008.04.18 56 9.9 rgb interface 9.9.1 general description the module uses 6, 16 and 18-bit parallel rgb inter face which includes: vs, hs, de, pclk, d[17:0]. the interface is activated after power on sequence (see section powe r on/off sequence) pixel clock (pclk) is running all the time without stopping and it is used to entering vs, hs, de and d[17:0] states when there is a rising edge of the pclk. the pclk cannot be used as continues internal clock for other func tions of the display module e.g. sleep in Cmode etc. vertical synchronization (vs) is used to tell when there is received a new frame of the display. this is negative (0, low) active and its state is read to the display module by a rising edge of he pclk signal. horizontal synchronization (hs) is used to tell whe n there is received a new line of the frame. this i s negative (0, low) active and its state is read to the display module by a rising edge of the pclk signal. data enable (de) is used to tell when there is rece ived a rgb information that should be transferred o n the display. this is a positive (1, high) active and its state is read to the display module by a rising edge of the pclk signal. d[17:0] (18-bit: r5-r0, g5-g0 and b5-b0; 16-bit: r4 -r0, g5-g0 and b4-b0) are used to tell what is the information of the image that is transferred on the display (when de= 1 and there is a rising edge of pclk). d[17:0] can be 0 (low) or 1 (high). these lines are read by a rising edge of th e pclk signal. the pclk cycle is described in the following figure . note: pclk is an unsynchronized signal (it can be sto pped). pclk vs, hs, de d[17:0] the host changes d[17:0], vs,hs and de lines when there is a falling edge of the pclk the driver read the d[17:0], vs,hs and de lines when there is a rising edge of the pclk fig. 9.9.1 pclk cycle
ST7787 v1.7 2008.04.18 57 9.9.2 general timing diagram fig. 9.9.2 rgb general timing diagram the image information must be correct on the displa y, when the timings are in range on the interface. however, the image information can be incorrect on the display, when timings are not out of range on t he interface (out of the range timings cannot on the host side). the cor rect image information must be displayed automatica lly (by the display module) on the next frame (vertical sync.) when the re is returned from out of the range to in range in terface timing.
ST7787 v1.7 2008.04.18 58 9.9.3 updating order on display active area (normal display mode on + sleep out) there is defined different kind of updating orders for display. these updating orders are controlled b y h/w (smx, smy) and s/w (mx, my, mv) bits. vertical active counter (0 ~ 319) vertical active counter (0 ~ 319) fig. 9.9.3 updating order when madctls mx=0 and my=0 fig. 9.9.4 updating order when madctls mx=1 and my=0 vertical active counter (0 ~ 319) vertical active counter (0 ~ 319) fig. 9.9.5 updating order when madctls mx=0 and my=1 fig. 9.9.6 updating order when madctls mx=1 and my=1
ST7787 v1.7 2008.04.18 63 table 9.9.1 rules for updating order condition horizontal counter vertical counter an active vs signal is received return to 0 return to 0 signal pixel information of the active area is rece ived increment by 1 no change an active hs signal between two active area lines return to 0 increment by 1 the horizontal counter is larger than 239 and the v ertical counter is larger than 319 return to 0 return to 0 note 1. pixel order is rgb on the display. note 2. data streaming direction from the host to t he display is described in the following figure. fig. 9.9.3 data streaming order for rgb interface 9.9.4 rgb interface bus width set all 4-kinds of bus width can be available during rg b interface mode (selected by colmod (3ah) command for 6-bit, 16-bit and 18-bit data width) vipf[3:0] d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus width 0101 r4 r3 r2 r1 r0 x g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 x 16-bit data 0110 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 18-bit data vipf[3:0] d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus width x x x x x x x x x x r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x g5 g4 g3 g2 g1 g0 x x 1110 x x x x x x x x x x b5 b4 b3 b2 b1 b0 x x 6-bit data note 1: when vipf[3:0]=1110, 6-bit data width of 3- times transfer is used to transmit 1 pixel data wit h the 18-bit color depth information. note 2: only vipf[3:0]= 0101 , 0110 and 1110 a re valid on rgb i/f, others are invalid. note 3. x dont care, but need to set vddi or dgnd level. 9.9.5 rgb interface mode set table 9.9.5.1 rgb interface mode set rgb i/f mode pclk de vs hs video data bus d[17:0] register for blanking porch setting reference clock for display rgb mode 1 used used used used used not used internal oscillator rgb mode 2 used used used used used used internal oscillator there are 2-kinds of rgb mode which is selected by rcm1 & rcm0 hardware pins. in rgb mode 1 (rcm1, rcm0 = 10), writing data to frame memory i s done by pclk and video data bus (d[17:0]), when de is high state. the external synchronization sign als (pclk, vs and hs) are used for internal display signals. so, controller (host) must always transfer pclk, vs, hs and de signals to ic. in rgb mode 2 (rcm1, rcm0 = 11), blanking porch setting of vs a nd hs signals are defined by rgbbpctr (b5h) command. de pin is used for data making. when de pi n is high, valid data is directly stored to frame m emory. in the contrast, if de pin is low the data of frame memory will keep same status.
ST7787 v1.7 2008.04.18 64 table 9.9.5.2 mcu & rgb interface comparisons table function rcm1, rcm0 rcm1, rcm0 "0x" "10" "11" 8080/ 6800 if + spi i/f rgb i/f + spi i/mode selection 1/f mode selection 1 mcu mode rgb mode 1 rgb mode 2 imx= imx="00" icm='0' icm='1' icm='0' icm='1' mode selection 2 8080/ 6800 if spi i/f rgb-1 i/f + spi i/f rgb-2 i/f + spi i/f motion /still selection motion or still picture still picture motion or still picture still picture motion or still picture still picture input data d[17:0] d0 d[17:0] sda h/w pin enable d[17:0] sda h/w pin enable csx d/cx = scl pclk d/cx = scl pclk d/cx = scl input signal wrx (r/wx), rdx (e) csx vs, hs, de csx vs, hs, de csx gram write cycle refer the wrx cycle refer scl refer pclk refer scl refer pclk refer scl gram read cycle refer internal oscillator refer internal oscillator refer pclk refer internal oscillator refer pclk refer internal oscillator command setting d[7:0] d0 sda sda sda sda smx, smy, srgb -if those register not change, those h/w pins are a lways valid. if those registers be changed, should be follow registers setting. -when power on or h/w reset, those function follow h/w pins setting first. te function -by command setting -by command setting -by command setting normal / partial mode -by command setting -by command setting -by command setting idle mode (idm h/w pin) -by idm h/w pin -idm on/off (39h/28h) are disable display on/ off (shut h/w pin) -by shut h/w pin -slpin(10h), slpout(11h), display on/off (29h/28h) are disable data inverter setting (rev h/w pin) -by command setting -dont care in this mode, but should be set to vddi or dgnd -by rev h/w pin -invon/off (21h/20h) are disable de h/w pin -the data latched by rising edge of pclk when de=1 -when display data coming the de signal should be vddi level -when de='0' area, the data of gram will keep the same status. rl h/w pin tb h/w pin -dont care in this mode, but should be set to vddi or dgnd -dont care in this mode, but should be set to vddi or dgnd -by h/w pin -no commands conflict blanking porch -dont care in this mode -control by de signal -control by rgbbpctr (b5h) colors format -control by ifpf[2:0] of colmod(3a) -control by vipf[3:0] of colmod(3a) note 1: rcm1 and rcm0 are h/w setting pins. note 2: in rgb + spi i/f (rcm="1x"), vs, hs, de, pclk and d[ 17:0] are hi-z by driver and can be stop for host, when icm='1'. note 3: in rgb + spi i/f (rcm="1x"), the data deliver via gram note 4: when power on driver ic should be detect smx, smy, srgb h/w setting note 5: when power on driver ic should be detect rcm 1, rcm0 h/w setting and get into the i/f mode. note 6: when power on driver ic should be detect lcm 1, lcm0 h/w setting and get into the setting mode.
ST7787 v1.7 2008.04.18 65 9.9.6 rgb interface timing diagram 9.9.6.1 general timings for rgb i/f fig. 9.9.6 general timing of rgb interface table 9.9.6.1 general timing for rgb i/f specification item symbol condition min type. max unit pixel low pulse width t pclklt 12 ns pixel high pulse width t pclkht 12 ns vertical sync. set-up time t vsst 15 ns vertical sync. hold time t vssht 15 ns horizontal sync. set-up time t hsst 15 ns horizontal sync. hold time t vssht 15 ns data enable set-up time t dest 15 ns data enable hold time t deht 15 ns data set-up time t dst 15 ns data hold time t dht 15 ns note 1: vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgnd =0v, ta=-30 to 70 (to +85 no damage) note 2: the input signal rise time and fall time (t r, tf) is specified at 15 ns or less. note 3. data lines can be set to high or low du ring blanking time C dont care. note 4. logic high and low levels are specified as 30% and 70% of vddi for input signals. note 5. hp is multiples of eight pclk.
ST7787 v1.7 2008.04.18 66 vs hs pclk data frame data n frame n+1 frame n+2 frame de * de ** frame data frame data don't care de * = rgb mode 1 de ** = rgb mode 2 ram write command (2ch) address set command (2ah, 2bh) data transfer (icm="1") data transfer (icm="1") fig. 9.9.7 ram access via spi interface in rgb mode note: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) com mand.
ST7787 v1.7 2008.04.18 67 9.9.6.2 rgb interface mode 1 timing diagram fig. 9.9.8 rgb mode 1 timing diagram note: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) com mand.
ST7787 v1.7 2008.04.18 68 fig. 9.9.9 vertical and horizontal timing of rgb in terface
ST7787 v1.7 2008.04.18 69 table 9.9.6.2 vertical and horizontal timing for rg b i/f specification item symbol condition min typ. max unit vertical timing vertical cycle period t vp 326 330 hs vertical low pulse width t vs 2 4 hs vertical front porch t vfp 2 4 hs vertical back porch t vbp 2 4 hs vertical data start line t vs + t vbp 4 8 hs vertical blanking period t vbl t vs + t vbp + t vfp 6 10 hs vertical active area t vdisp 320 hs vertical refresh rate t vrr frame rate 61.75 65 68.25 hz horizontal timing horizontal cycle period t hp 272 512 pclk horizontal low pulse width t hs 2 256 pclk horizontal front porch t hfp 2 256 pclk horizontal back porch t hbp 2 256 pclk t hs + t hbp 30 256 pclk horizontal data start point ff hs + f hbp 1.0 us horizontal blanking period t hbl 32 256 pclk horizontal active area t hdisp 240 pclk t pclkcyc 33.3 174 ns pixel clock cycle f pclkcyc tvrr=65hz 5.8 30.0 mhz note 1. vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgnd =0v, ta=-30 to 70 (to +85 no damage) note 2. data lines can be set to high or low du ring blanking time C dont care. note 3. hp is multiples of eight pclk.
ST7787 v1.7 2008.04.18 70 9.9.6.3 rgb interface mode 2 timing diagram vs hs de hs pclk de data bus latch data v back porch (t vs +t vbp ) 1 frame (t vp ) v front porch (t vfp ) 1 line (t hp ) h back porch (t hs +t hbp ) valid data (t hdisp ) h front porch (t hfp ) invalid invalid invalid d n d n d 1d 1 d 2 d 2 d 3 d 3 ?1" ?1" fig. 9.9.10 rgb mode 2 timing diagram fig. 9.9.11 rgb mode 2 vertical timing diagram note: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) com mand. hs d[17:0] pclk t hfp =10 pclk t hs +t hbp =10 pclk t hdisp =240 pclk t hp = 260 pclk horizontal timing for rgb i/f invalid invalid fig. 9.9.12 rgb mode 2
ST7787 v1.7 2008.04.18 71 fig. 9.9.13 rgb mode 2 idle mode timing diadram note: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) com mand. fig. 9.9.14 vertical and horizontal in rgb interfac e
ST7787 v1.7 2008.04.18 72 table 9.9.6.3 vertical and horizontal timing for rg b i/f specification item symbol condition min type. max unit vertical timing vertical cycle period t vp 323 324 hs vertical low pulse width t vs 1 4 hs vertical front porch t vfp 1 1 1023 hs vertical back porch t vbp 1 1023 hs vertical data start line tvs + tvbp 2 3 1023 hs vertical blanking period t vbl tvs + tvbp + tvfp 3 4 1023 hs vertical active area t vdisp 320 hs vertical refresh rate tvrr frame rate 61.75 65 68.2 5 hz horizontal timing horizontal cycle period t hp 243 260 511 pclk horizontal low pulse width t hs 1 63 pclk horizontal front porch t hfp 1 63 pclk horizontal back porch t hbp 1 63 pclk ths + thbp 1 10 63 pclk horizontal data start point ff hs + fhbp 0.196 us horizontal blanking period t hbl 3 20 256 pclk horizontal active area t hdisp 240 pclk t pclkcyc 33.3 182 196 ns pixel clock cycle f pclkcyc tvrr=65hz 5.1 5.48 30 mhz note 1. vddi=1.65 to 3.3v, vdd=2.45 to 3.3v, agnd=dgnd =0v, ta=-30 to 70 (to +85 no damage) note 2. data lines can be set to high or low du ring blanking time C dont care. note 3. hp is multiples of eight pclk.
ST7787 v1.7 2008.04.18 73 9.9.6.4 power on sequence on rgb mode 2 the driver operates power up and display on by vdd, vddi, shut, vs, hs, de, pclk on rgb mode 2 as show as following figure. vdd resx shut pclk hs de vs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 display high voltage display source output vcom output gate output internal counter internal oscillator t vdd-vddi t rs-sh t vdd-sh t pclk-sh t sh-lcd t sh-on display on normal display normal display normal display blanking display (over 1 frame) vdd vddi resx shut pclk hs de vs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 display high voltage display source output vcom output gate output internal counter internal oscillator t vdd-vddi t rs-sh t vdd-sh t pclk-sh t sh-lcd t sh-on display on normal display normal display normal display blanking display (over 1 frame) fig. 9.9.15 power-on sequence in rgb mode 2 table 9.9.6.4 power on ac characteristics characteristics symbol min typ max unit remark vdd on to vddi on tvdd-vddi 0 ns vddi/vdd on to falling edge of shut tvdd-sh 1 ms resx to falling of shut trs-sh 10 us signals input to falling edge of shut * tclk-sh 1 pclk note1 falling edge of shut to lcd power on tsh-lcd 120 ms falling edge of shut to display start tsh-on 10 v s note 1: signals mean vs, hs, de and pclk signal. note 2: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) command.
ST7787 v1.7 2008.04.18 74 9.9.6.5 power off sequence on rgb mode 2 the driver operates power off and display off by vd d, vddi, shut, vs, hs and de on rgb mode 2 as show as following figure. resx shut pclk hs de vs display high voltage display source output vcom output gate output internal counter internal oscillator display off normal display display on normal display normal display 0v 0v blanking display (over 1 frame) t vdd-vddi t off-vdd t sh-off resx shut pclk hs de vs display high voltage display source output vcom output gate output internal counter internal oscillator display off normal display display on normal display normal display 0v 0v blanking display (over 1 frame) t vdd-vddi t off-vdd t sh-off fig. 9.9.16 power-off seqnence in rgb mode 2 table 9.9.6.5 power off ac characteristics characteristics symbol min typ max unit remark vddi on to vdd on tvdd-vddi 0 ns signals input to vddi/vdd off tsh-off 1 us note1 rising edge of shut to display off tsh-off 2 vs note 1: signals mean vs, hs, de and pclk signal. note 2: dp=0, ep=0, hsp=0 and vsp=0 of rgbctr (b0h) command.
ST7787 v1.7 2008.04.18 75 9.9.7 rgb data color coding 9.9.7.1 16-bit/pixel color order on the rgb interfa ce note 1: the data order is as follows, msb=d17, lsb=d0 a nd picture data is msb=bit5, lsb=bit0 for green data and msb=bit4, lsb=bit0 for red and blue data. note 2. - dont care, but need set to vddi or dgnd level. pclk
ST7787 v1.7 2008.04.18 76 9.9.7.2 18-bit/pixel color order on the rgb interfa ce note 1: the data order is as follows, msb=d17, lsb=d0 a nd picture data is msb=bit5, lsb=bit0 for red, green and blue data. note 2. - dont care, but need set to vddi or dgnd level. pclk
ST7787 v1.7 2008.04.18 77 9.9.7.3 6-bit/pixel color order on the rgb interfac e g1,bit3 g1,bit2 g1,bit1 g1,bit0 rcm[1:0] vs ? 1 ? ? 10 ? or ? 11 ? wrx d9 d8 pixeln pixeln+1 18bits 18bits r1 g1 b1 r2 g2 b2 r3 g3 b3 framememory r1,bit3 r1,bit2 r1,bit1 r1,bit0 d7 d6 d5 d4 d3 d2 d1 d0 b1,bit3 b1,bit2 b1,bit1 b1,bit0 g2,bit3 g2,bit2 g2,bit1 g2,bit0 r2,bit3 r2,bit2 r2,bit1 r2,bit0 d17 d16 r1,bit4 r2,bit4 g1,bit5 g1,bit4 g2,bit5 g2,bit4 b1,bit4 hs de ? 1 ? resx ? 1 ? ? 1 ? r1,bit5 r2,bit5 b1,bit5 note 1: the data order is as follows, msb=d17, lsb=d0 a nd picture data is msb=bit5, lsb=bit0 for red, green and blue data. note 2. - dont care, but need set to vddi or dgnd level. pclk
ST7787 v1.7 2008.04.18 78 9.10 display data ram 9.10.1 configuration the display module has an integrated 240x320x18-bit graphic type static ram. this 1382,400-bit memory allows to store on-chip a 240xrgbx320 image with an 18-bpp resoluti on (262k-color). there will be no abnormal visible effect on the dis play when there is a simultaneous panel read and in terface read or write to the same location of the frame memory. fig. 9.10.1 display data ram organization
ST7787 v1.7 2008.04.18 79 9.10.2 memory to display address mapping 9.10.2.1 when using 240rgb x 320 resolution (smx=sm y=srgb=0) -------- gate out s1 s2 s3 s4 s5 s6 -------- s715 s716 s717 s718 s719 s720 my=' 0 ' my=' 1 ' ml=' 0 ' ml=' 1 ' 1 0 319 r0 g0 b0 r1 g1 b1 -------- r238 g238 b238 r239 g239 b239 0 319 2 1 318 -------- 1 318 3 2 317 -------- 2 317 4 3 316 -------- 3 316 5 4 315 -------- 4 315 6 5 314 -------- 5 314 7 6 313 -------- 6 313 8 7 312 -------- 7 312 || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | || | | | 313 312 7 -------- 312 7 314 313 6 -------- 313 6 315 314 5 -------- 314 5 316 315 4 -------- 315 4 317 316 3 -------- 316 3 318 317 2 -------- 317 2 319 318 1 -------- 318 1 320 319 0 -------- 319 0 mx=' 0 ' -------- mx=' 1 ' -------- pixel 1 pixel 2 pixel 239 pixel 240 source out rgb=0 rgb=1 rgb=0 rgb=1 rgb order rgb=0 rgb=1 rgb=0 rgb=1 ra sa ca 0 1 238 239 239 238 1 0 note ra = row address, ca = column address sa = scan address mx = mirror x-axis (column address direction parame ter), d6 parameter of madctl command my = mirror y-axis (row address direction parameter ), d7 parameter of madctl command mv =scan direction parameter, d4 parameter of madct l command rgb = red, green and blue pixel position change, d3 parameter of madctl command
ST7787 v1.7 2008.04.18 80 9.10.3 normal display on or partial mode on, vertic al scroll off 9.10.3.4 when using 240rgb x 320 resolution in this mode, contents of the frame memory within a n area where column pointer is 00h to efh and page pointer is 00h to 13fh is displayed. to display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). example for normal display on (mx=my=ml=0 ,sm x=smy=0) 2). example for partial display on (psl[7:0]=04h,pe l[7:0]=13bh, mx=mv=ml=0 ,smx=smy=0) 240 columns 00h 01h ---- ---- ---- ---- ---- eeh efh 00h 00 01 02 03 0w 0x 0y 0z 1 01h 10 11 12 13 1w 1x 1y 1z 2 02h 20 21 22 2x 2y 2z 3 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | 13dh x0 x1 x2 xx xy xz 318 13eh y0 y1 y2 y3 yw yx yy yz 319 13fh z0 z1 z2 z3 zw zx zy zz 320 240 x 320 x18 bit fram e ram 240 columns 320 lines scan order 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 20 21 22 2x 2y 2z g3 30 31 32 3x 3y 3z | 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s0 sz | u0 u1 uy uz | v0 v1 v2 vx vy vz | w0 w1 w2 wx wy wz | x0 x1 x2 xx xy xz g318 y0 y1 y2 y3 yw yx yy yz g319 z0 z1 z2 z3 zw zx zy zz g320 240 rgb x 320 lcd panel non-display area =4 lines display area =312 lines non-display area =4lines 240 columns 00h 01h ---- ---- ---- ---- ---- eeh efh 00h 00 01 02 03 0w 0x 0y 0z 1 01h 10 11 12 13 1w 1x 1y 1z 2 02h 20 21 22 2x 2y 2z 3 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | 13dh x0 x1 x2 xx xy xz 318 13eh y0 y1 y2 y3 yw yx yy yz 319 13fh z0 z1 z2 z3 zw zx zy zz 320 240 x 320 x18 bit fram e ram 240 columns 320 lines display area =320 lines scan order 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 20 21 22 2x 2y 2z g3 30 31 32 3x 3y 3z | 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s0 sz | u0 u1 uy uz | v 0 v 1 v 2 v x v y v z | w 0 w 1 w 2 w x wy wz | x 0 x 1 x 2 x x x y x z g318 y 0 y 1 y 2 y 3 y w y x y y y z g319 z 0 z 1 z 2 z 3 z w z x z y z z g320 240 r g b x 320 240 r g b x 320 240 r g b x 320 240 r g b x 320 lc d panel lc d panel lc d panel lc d panel
ST7787 v1.7 2008.04.18 81 9.10.4 vertical scroll mode there is vertical scrolling, which are determined b y the commands vertical scrolling definition (33h ) and vertical scrolling start address (37h). fig. 9.10.2 difference between scrolling and origin al
ST7787 v1.7 2008.04.18 82 9.10.4.1 when using 240rgb x 320 resolution when vertical scrolling definition parameters (tfa+ vsa+bfa)=320. in this case, scrolling is applied as shown below. 1). example for tfa =3, vsa=315, bfa=2, ssa=4, ml=0 : scrolling 2). example for tfa =3, vsa=315, bfa=2, ssa=4, ml=1 : scrolling: tfa and bft are exchanged 240 columns 240 columns 320 lines scan order bfa vsa tfa 00h 01h ---- ---- ---- ---- ---- eeh efh 00h 00 01 02 03 0w 0x 0y 0z 320 01h 10 11 12 13 1w 1x 1y 1z 319 02h 20 21 22 2x 2y 2z 318 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | 13dh x0 x1 x2 xx xy xz 3 13eh y0 y1 y2 y3 yw yx yy yz 2 13fh z0 z1 z2 z3 zw zx zy zz 1 240 x 320 x18 bit fram e ram ssa 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 w 0 w 1 w 2 w x w y w z g3 20 21 22 2x 2y 2z | 30 31 32 3x 3y 3z | 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s0 sz | u0 u1 uy uz | v 0 v 1 v 2 v x v y v z | x 0 x 1 x 2 x x x y x z g318 y 0 y 1 y 2 y 3 yw y x y y y z g319 z 0 z 1 z 2 z 3 zw z x z y z z g320 240 r g b x 320 240 r g b x 320 240 r g b x 320 240 r g b x 320 lc d panel lc d panel lc d panel lc d panel 240 columns 240 columns 320 lines scan order tfa vsa bfa 00h 01h ---- ---- ---- ---- ---- eeh efh 00h 00 01 02 03 0w 0x 0y 0z 1 01h 10 11 12 13 1w 1x 1y 1z 2 02h 20 21 22 2x 2y 2z 3 | 30 31 32 3x 3y 3z | | 40 41 42 4x 4y 4z | | 50 51 5y 5z | | 60 6z | | | | | | | | | | s0 sz | | u0 u1 uy uz | | v0 v1 v2 vx vy vz | | w0 w1 w2 wx wy wz | 13dh x0 x1 x2 xx xy xz 318 13eh y0 y1 y2 y3 yw yx yy yz 319 13fh z0 z1 z2 z3 zw zx zy zz 320 240 x 320 x18 bit fram e ram 00 01 02 03 0w 0x 0y 0z g1 10 11 12 13 1w 1x 1y 1z g2 20 21 22 2x 2y 2z g3 40 41 42 4x 4y 4z | 50 51 5y 5z | 60 6z | || | | s 0 s z | u0 u1 uy uz | v 0 v 1 v 2 v x v y v z | w 0 w 1 w2 w x w y wz | x 0 x1 x 2 x x xy x z | 30 31 32 3x 3y 3z g318 y 0 y1 y 2 y3 yw y x yy y z g319 z 0 z1 z 2 z3 zw z x zy z z g320 240 r g b x 320 240 r g b x 320 240 r g b x 320 240 r g b x 320 lcd panel lcd panel lcd panel lcd panel ssa
ST7787 v1.7 2008.04.18 83 9.10.5 vertical scroll example case 1: tfa + vsa + bfa ? 320 n/a. do not set tfa + vsa + bfa 320. in that case, unexpected picture will be shown . case 2: tfa + vsa + bfa=320 (scrolling) example1) when madctl parameter ml=0, tfa=0, vsa= 320, bfa=0 and vscsad=80. example2) when madctl parameter ml=1, tfa=30, vsa =290, bfa=0 and vscsad=80.
ST7787 v1.7 2008.04.18 84 9.11 address counter the address counter sets the addresses of the displ ay data ram for writing and reading. data is written pixel-wise into the ram matrix of d river. the data for one pixel or two pixels is coll ected (rgb 6-6-6-bit), according to the data formats. as soon as this pixe l-data information is complete the write access i s activated on the ram. the locations of ram are addressed by the address p ointers. the address ranges are x=0 to x=239 (efh) and y=0 to y=319 (13fh). addresses outside these ranges are no t allowed. before writing to the ram a window must be defined into which will be written. the window is programmable v ia the command registers xs, ys designating the sta rt address and xe, ye designating the end address. for example the whole display contents will be writ ten, the window is defined by the following values: xs=0 (0h) ys=0 (0h) and xe=239 (efh), ye=319 (13fh). in vertical addressing mode (mv=1), the y-address i ncrements after each byte, after the last y-address (y=ye), y wraps around to ys and x increments to address the next c olumn. in horizontal addressing mode (v=0), the x-a ddress increments after each byte, after the last x-addres s (x=xe), x wraps around to xs and y increments to address the next row. after the every last address (x=xe and y=ye) t he address pointers wrap around to address (x=xs an d y=ys). for flexibility in handling a wide variety of displ ay architectures, the commands caset, raset and madctl (see section 10 command list), define flags mx and my, w hich allows mirroring of the x-address and y-addres s. all combinations of flags are allowed. section 9.12 sho w the available combinations of writing to the disp lay ram. when mx, my and mv will be changed the data bust be rewritte n to the display ram. for each image condition, the controls for the colu mn and row counters apply as section. 9.12 below: condition column counter row counter when ramwr/ramrd command is accepted return to start column (xs) return to start row (ys) complete pixel read / write action increment by 1 no change the column counter value is larger than end column (xe) return to start column (xs) increment by 1 the column counter value is larger than end column (xe) and the row counter value is larger than end row (ye) return to start column (xs) return to start row (ys) 9.12. memory data write/ read direction the data is written in the order illustrated above. the counter which dictates where in the physical m emory the data is to be written is controlled by memory data access contro l command, bits b5 (mv), b6 (mx), b7 (my) as descr ibed below. fig. 9.12.1 data streaming order
ST7787 v1.7 2008.04.18 85 9.12.1 when 240rgbx320 physical row point madctl (36h) mv mx my caset raset 0 0 0 direct to physical column pointer direct to p hysical row pointer 0 0 1 direct to physical column pointer direct to ( 319-physical row pointer) 0 1 0 direct to (239-physical column pointer) direc t to physical row pointer 0 1 1 direct to (239-physical column pointer) direc t to (319-physical row pointer) 1 0 0 direct to physical row pointer direct to phys ical column pointer 1 0 1 direct to (319-physical row pointer) direct t o physical column pointer 1 1 0 direct to physical row pointer direct to (239 -physical column pointer) 1 1 1 direct to (319-physical row pointer) direct t o (239-physical column pointer) note: data is always written to the frame memory in the same order, regardless of the memory write dir ection set by madctl bits b7 (my), b6 (mx), b5 (mv). the write order for each pi xel unit is one pixel unit represents 1 column and 1page counte r value on the frame memory.
ST7787 v1.7 2008.04.18 86 9.12.2 frame data write direction according to the madctl parameters (mv, mx and my) madctl parameter display data direction mv mx my image in the host (mpu) image in the driver (ddram) normal 0 0 0 y-mirror 0 0 1 x-mirror 0 1 0 x-mirror y-mirror 0 1 1 x-y exchange 1 0 0 x-y exchange y-mirror 1 0 1 x-y exchange x-mirror 1 1 0 x-y exchange x-mirror y-mirror 1 1 1 h/w position (0,0) f h/w position (0,0) f h/w position (0,0) x-y address (0,0) x: raset y: caset b h/w position (0,0) x-y address (0,0) x: raset y: caset f h/w position (0,0) f b x-y address (0,0) x: caset y: raset b f h/w position (0,0) x-y address (0,0) x: caset y: raset h/w position (0,0) x-y address (0,0) x: caset y: raset b f b f h/w position (0,0) x-y address (0,0) x: caset y: raset b f b f b f b f b f b f b f b f b f b x-y address (0,0) x: raset y: caset b x-y address (0,0) x: raset y: caset
ST7787 v1.7 2008.04.18 87 9.13 tearing effect output line the tearing effect output line supplies to the mpu a panel synchronization signal. this signal can be enabled or disabled by the tearing effect line off & on commands. the m ode of the tearing effect signal is defined by the parameter of the tearing effect line on command. the signal can be u sed by the mpu to synchronize frame memory writing when displaying video images. 9.13.1 tearing effect line modes mode 1 , the tearing effect output signal consists of v-bl anking information only: tvdh= the lcd display is not updated from the frame memory tvdl= the lcd display is updated from the frame mem ory (except invisible line C see below) mode 2 , the tearing effect output signal consists of v-bl anking and h-blanking information, there is one v-s ync and 320 h-sync pulses per field. thdh= the lcd display is not updated from the frame memory thdl= the lcd display is updated from the frame mem ory (except invisible line C see above) note: during sleep in mode, the tearing output pin is active low.
ST7787 v1.7 2008.04.18 88 9.13.2 tearing effect line timings the tearing effect signal is described below: table 9.13.1 ac characteristics of tearing effect s ignal idle mode off (frame rate = 58.9 hz) symbol parameter min max unit description t vdl vertical timing low duration 13 - ms t vdh vertical timing high duration 1000 - s t hdl horizontal timing low duration 33 - s t hdh horizontal timing low duration 25 500 s note: the timings in table 9.3.1 apply when madctl ml =0 and ml=1 the signals rise and fall times (tf, tr) are stipu lated to be equal to or less than 15ns. the tearing effect output line is fed back to the m pu and should be used as shown below to avoid teari ng effect:
ST7787 v1.7 2008.04.18 89 9.13.3 example 1: mpu write is faster than panel read . time time time 1 st 320 nd 1 st 320 nd mcu to memory te output signal memory to lcd image on lcd data write to frame memory is now synchronized to t he panel scan. it should be written during the vert ical sync pulse of the tearing effect output line. this ensures that d ata is always written ahead of the panel scan and e ach panel frame refresh has a complete new image: b
ST7787 v1.7 2008.04.18 90 9.13.4 example 2: mpu write is slower than panel read . the mpu to frame memory write begins just after pan el read has commenced i.e. after one horizontal syn c pulse of the tearing effect output line. this allows time for th e image to download behind the panel read pointer a nd finishing download during the subsequent frame before the rea d pointer catches the mpu to frame memory write p osition. b
ST7787 v1.7 2008.04.18 91 9.14 preset values ST7787 will set preset values on our production lin e for each display module. any of these preset valu es do not need customers sw support. 9.15 power on/off sequence the power on/off sequence is illustrated below: 9.15.1 uncontrolled power off the uncontrolled power off means a situation when e .g. there is removed a battery without the controll ed power off sequence. there will not be any damages for the dis play module or the display module will not cause an y damages for the host or lines of the interface. 2. at an uncontrolled power off the display will go blank and there will not be any visible effects wi thin (tbd) second on the display (blank display) and remains blank until po wer on sequence powers it up.
ST7787 v1.7 2008.04.18 92 9.16 power level definition 9.16.1 power level 6 level modes are defined they are in order of maxi mum power consumption to minimum power consumption: 1. normal mode on (full display), idle mode off, sl eep out. in this mode, the display is able to show maximum 2 62,144 colors. 2. partial mode on, idle mode off, sleep out. in this mode part of the display is used with maxim um 262,144 colors. 3. normal mode on (full display), idle mode on, slee p out. in this mode, the full display area is used but wit h 8 colors. 4. partial mode on, idle mode on, sleep out. in this mode, part of the display is used but with 8 colors. 5. sleep in mode in this mode, the dc: dc converter, internal oscill ator and panel driver circuit are stopped. only the mcu interface and memory works with vddi power supply. contents of th e memory are safe. 6. power off mode in this mode, both vdd and vddi are removed. note: transition between modes 1-5 is controllable by mcu commands. mode 6 is entered only when both power supplies are removed.
ST7787 v1.7 2008.04.18 93 9.16.2 power flow chart sleep out normal display mode on idle mode off sleep in normal display mode on idle mode off sleep out normal display mode on idle mode on sleep in normal display mode on idle mode on sleep out partial display mode on idle mode off sleep in partial display mode on idle mode off sleep out partial display mode on idle mode on sleep in partial display mode on idle mode on slp in slp in slp in slp in slp out slp out slp out slp out idm on idm off idm on idm off ptl on nor on ptl on nor on idm on idm off ptl on nor on ptl on nor on idm on idm off power on sequence hw reset sw reset normal display mode on = nor on partial display mode on = ptl on idle mode off = idm off idle mode on = idm on sleep out = slp out sleep in = slp in note 1: there is not any abnormal visual effect whe n there is changing from one power mode to another power mode. note 2: there is not any limitation, which is not s pecified by this spec, when there is changing from one power mode to another power mode.
ST7787 v1.7 2008.04.18 94 9.17 reset 9.17.1 reset table (240rgb x320) item after power on after hardware reset after software reset frame memory random no change no change sleep in/out in in in display on/off off off off display mode (normal/partial) normal normal normal display inversion on/off off off off vsyncin on on on vsyncout off off off display idle mode on/off off off off column: start address (xs) 0000h 0000h 0000h column: end address (xe) 00efh 00efh 00efh (239d) (when mv=0) 013fh (319d) (when mv=1) row: start address (ys) 0000h 0000h 0000h row: end address (ye) 013fh 013fh 013fh (319d) (when mv=0) 00efh (239d) (when mv=1) gamma setting gc0 gc0 gc0 rgb for 4k and 65k color mode see section 9.19 see section 9.19 no change partial: start address (psl) 0000h 0000h 0000h partial: end address (pel) 013fh 013fh 013fh scroll: vertical scrolling off off off scroll: top fixed area (tfa) 0000h 0000h 0000h scroll: scroll area (vsa) 0140h 0140h 0140h scroll: bottom fixed area (bfa) 0000h 0000h 0000h scroll start address (ssa) 0000h 0000h 0000h tearing: on/off off off off tearing effect mode *3) 0 (mode1) 0 (mode1) 0 (mode 1) memory data access control (my/mx/mv/ml/rgb) 0/0/0/0/0 0/0/0/0/0 no change interface pixel color format 6 (18-bit/pixel) 6 (18 -bit/pixel) no change rddpm 08h 08h 08h rddmadctl 00h 00h no change rddcolmod 6 (18-bit/pixel) 6 (18-bit/pixel) no change rddim 00h 00h 00h rddsm 00h 00h 00h rddsdr 00h 00h 00h id1 38h 38h 38h id2 nv value nv value nv value id3 nv value nv value nv value notes 1. there will be no abnormal visible effects on the display when s/w or h/w reset is applied. notes:2. powered-on reset finishes within 10 s after both vdd & vddi are applied. notes:3. te mode 1 means tearing effect output line consists of v-blanking information only.
ST7787 v1.7 2008.04.18 95 9.17.2 module input/output pins 9.17.2.1 output or bi-directional (i/o) pins output or bi-directional pins after power on after hardware reset after software reset te low low low d7 to d0 (output driver) high-z (inactive) high-z ( inactive) high-z (inactive) note: there will be no output from d7-d0 during pow er on/off sequence, hardware reset and software res et. 9.17.2.2 input pins input pins during power on process after power on after hardware reset after software reset during power off process resx see 9.15 input valid input valid input valid s ee 9.15 csx input invalid input valid input valid input val id input invalid d/cx input invalid input valid input valid input va lid input invalid wrx input invalid input valid input valid input val id input invalid rdx input invalid input valid input valid input val id input invalid d7 to d0 input invalid input valid input valid inpu t valid input invalid p/sx input invalid input valid input valid input va lid input invalid
ST7787 v1.7 2008.04.18 96 9.17.3 reset timing table 9.18.3.1 reset input timing vss=0v, vddi=1.65v to 1.95v, vdd=2.45v to 2.9v,ta = -30 to 70 ) symbol parameter related pins min typ max note unit t resw *1) reset low pulse width resx 30 - - - us t rest *2) reset complete time - 120 - - ms note 1) spike due to an electrostatic discharge on r esx line does not cause irregular system reset accord ing to the table below. note 2. during the resetting period, the display wi ll be blanked (the display is entering blanking seq uence, which maximum time is 120 ms, when reset starts in sleep out Cmode. the display remains the blank state in sleep in Cm ode) and then return to default condition for h/w reset. note 3. during reset complete time, id2 and vcomof v alue in otp will be latched to internal register dur ing this period. this loading is done every time when there is h/w r eset complete time (trest) within 120ms after a risin g edge of resx. note 4. spike rejection also applies during a valid reset pulse as shown below:
ST7787 v1.7 2008.04.18 97 9.18 color depth conversion look up tables 9.18.1 4096 and 65536 color to 262,144 color look up table input data color look up table outputs frame memory data (6-bit) default value after h/w reset rgbset parameter 4k color 65k color r 005 r 004 r 003 r 002 r 001 r 000 000000 1 0000 00000 r 015 r 014 r 013 r 012 r 011 r 010 000011 2 0001 00001 r 025 r 024 r 023 r 022 r 021 r 020 000101 3 0010 00010 r 035 r 034 r 033 r 032 r 031 r 030 000111 4 0011 00011 r 045 r 044 r 043 r 042 r 041 r 040 001001 5 0100 00100 r 055 r 054 r 053 r 052 r 051 r 050 001011 6 0101 00101 r 065 r 064 r 063 r 062 r 061 r 060 001101 7 0110 00110 r 075 r 074 r 073 r 072 r 071 r 070 001111 8 0111 00111 r 085 r 084 r 083 r 082 r 081 r 080 010001 9 1000 01000 r 095 r 094 r 093 r 092 r 091 r 090 010011 10 1001 01001 r 105 r 104 r 103 r 102 r 101 r 100 010101 11 1010 01010 r 115 r 114 r 113 r 112 r 111 r 110 010111 12 1011 01011 r 125 r 124 r 123 r 122 r 121 r 120 011001 13 1100 01100 r 135 r 134 r 133 r 132 r 131 r 130 011011 14 1101 01101 r 145 r 144 r 143 r 142 r 141 r 140 011101 15 1110 01110 r 155 r 154 r 153 r 152 r 151 r 150 011111 16 1111 01111 r 165 r 164 r 163 r 162 r 161 r 160 100001 17 10000 r 175 r 174 r 173 r 172 r 171 r 170 100011 18 10001 r 185 r 184 r 183 r 182 r 181 r 180 100101 19 10010 r 195 r 194 r 193 r 192 r 191 r 190 100111 20 10011 r 205 r 204 r 203 r 202 r 201 r 200 101001 21 10100 r 215 r 214 r 213 r 212 r 211 r 210 101011 22 10101 r 225 r 224 r 223 r 222 r 221 r 220 101101 23 10110 r 235 r 234 r 233 r 232 r 231 r 230 101111 24 10111 r 245 r 244 r 243 r 242 r 241 r 240 110001 25 11000 r 255 r 254 r 253 r 252 r 251 r 250 110011 26 11001 r 265 r 264 r 263 r 262 r 261 r 260 110101 27 11010 r 275 r 274 r 273 r 272 r 271 r 270 110111 28 11011 r 285 r 284 r 283 r 282 r 281 r 280 111001 29 11100 r 295 r 294 r 293 r 292 r 291 r 290 111011 30 11101 r 305 r 304 r 303 r 302 r 301 r 300 111101 31 11110 red r 315 r 314 r 313 r 312 r 311 r 310 111111 32 not used 11111
ST7787 v1.7 2008.04.18 98 look up table input data color look up table outputs frame memory data (6-bit) default value after h/w reset rgbset parameter 4k color 65k color g 005 g 004 g 003 g 002 g 001 g 000 000000 33 0000 000000 g 015 g 014 g 013 g 012 g 011 g 010 000001 34 0001 000001 g 025 g 024 g 023 g 022 g 021 g 020 000010 35 0010 000010 g 035 g 034 g 033 g 032 g 031 g 030 000011 36 0011 000011 g 045 g 044 g 043 g 042 g 041 g 040 000100 37 0100 000100 g 055 g 054 g 053 g 052 g 051 g 050 000101 38 0101 000101 g 065 g 064 g 063 g 062 g 061 g 060 000110 39 0110 000110 g 075 g 074 g 073 g 072 g 071 g 070 000111 40 0111 000111 g 085 g 084 g 083 g 082 g 081 g 080 001000 41 1000 001000 g 095 g 094 g 093 g 092 g 091 g 090 001001 42 1001 001001 g 105 g 104 g 103 g 102 g 101 g 100 001010 43 1010 001010 g 115 g 114 g 113 g 112 g 111 g 110 001011 44 1011 001011 g 125 g 124 g 123 g 122 g 121 g 120 001100 45 1100 001100 g 135 g 134 g 133 g 132 g 131 g 130 001101 46 1101 001101 g 145 g 144 g 143 g 142 g 141 g 140 001110 47 1110 001110 g 155 g 154 g 153 g 152 g 151 g 150 001111 48 1111 001111 g 165 g 164 g 163 g 162 g 161 g 160 010000 49 010000 g 175 g 174 g 173 g 172 g 171 g 170 010001 50 010001 g 185 g 184 g 183 g 182 g 181 g 180 010010 51 010010 g 195 g 194 g 193 g 192 g 191 g 190 010011 52 010011 g 205 g 204 g 203 g 202 g 201 g 200 010100 53 010100 g 215 g 214 g 213 g 212 g 211 g 210 010101 54 010101 g 225 g 224 g 223 g 222 g 221 g 220 010110 55 010110 g 235 g 234 g 233 g 232 g 231 g 230 010111 56 010111 g 245 g 244 g 243 g 242 g 241 g 240 011000 57 011000 g 255 g 254 g 253 g 252 g 251 g 250 011001 58 011001 g 265 g 264 g 263 g 262 g 261 g 260 011010 59 011010 g 275 g 274 g 273 g 272 g 271 g 270 011011 60 011011 g 285 g 284 g 283 g 282 g 281 g 280 011100 61 011100 g 295 g 294 g 293 g 292 g 291 g 290 011101 62 011101 g 305 g 304 g 303 g 302 g 301 g 300 011110 63 011110 green g 315 g 314 g 313 g 312 g 311 g 310 011111 64 not used 011111
ST7787 v1.7 2008.04.18 99 look up table input data color look up table outputs frame memory data (6-bit) default value after h/w reset rgbset parameter 4k color 65k color g 325 g 324 g 323 g 322 g 321 g 320 100000 65 100000 g 335 g 334 g 333 g 332 g 331 g 330 100001 66 100001 g 345 g 344 g 343 g 342 g 341 g 340 100010 67 100010 g 355 g 354 g 353 g 352 g 351 g 350 100011 68 100011 g 365 g 364 g 363 g 362 g 361 g 360 100100 69 100100 g 375 g 374 g 373 g 372 g 371 g 370 100101 70 100101 g 385 g 384 g 383 g 382 g 381 g 380 100110 71 100110 g 395 g 394 g 393 g 392 g 391 g 390 100111 72 100111 g 405 g 404 g 403 g 402 g 401 g 400 101000 73 101000 g 415 g 414 g 413 g 412 g 411 g 410 101001 74 101001 g 425 g 424 g 423 g 422 g 421 g 420 101010 75 101010 g 435 g 434 g 433 g 432 g 431 g 430 101011 76 101011 g 445 g 444 g 443 g 442 g 441 g 440 101100 77 101100 g 455 g 454 g 453 g 452 g 451 g 450 101101 78 101101 g 465 g 464 g 463 g 462 g 461 g 460 101110 79 101110 g 475 g 474 g 473 g 472 g 471 g 470 101111 80 101111 g 485 g 484 g 483 g 482 g 481 g 480 110000 81 110000 g 495 g 494 g 493 g 492 g 491 g 490 110001 82 110001 g 505 g 504 g 503 g 502 g 501 g 500 110010 83 110010 g 515 g 514 g 513 g 512 g 511 g 510 110011 84 110011 g 525 g 524 g 523 g 522 g 521 g 520 110100 85 110100 g 535 g 534 g 533 g 532 g 531 g 530 110101 86 110101 g 545 g 544 g 543 g 542 g 541 g 540 110110 87 110110 g 555 g 554 g 553 g 552 g 551 g 550 110111 88 110111 g 565 g 564 g 563 g 562 g 561 g 560 111000 89 111000 g 575 g 574 g 573 g 572 g 571 g 570 111001 90 111001 g 585 g 584 g 583 g 582 g 581 g 580 111010 91 111010 g 595 g 594 g 593 g 592 g 591 g 590 111011 92 111011 g 605 g 604 g 603 g 602 g 601 g 600 111100 93 111100 g 615 g 614 g 613 g 612 g 611 g 610 111101 94 111101 g 625 g 624 g 623 g 622 g 621 g 620 111110 95 111110 green g 635 g 634 g 633 g 632 g 631 g 630 111111 96 not used 111111
ST7787 v1.7 2008.04.18 100 look up table input data color look up table outputs frame memory data (6-bit) default value after h/w reset rgbset parameter 4k color 65k color b 005 b 004 b 003 b 002 b 001 b 000 000000 97 0000 00000 b 015 b 014 b 013 b 012 b 011 b 010 000011 98 0001 00001 b 025 b 024 b 023 b 022 b 021 b 020 000101 99 0010 00010 b 035 b 034 b 033 b 032 b 031 b 030 000111 100 0011 00011 b 045 b 044 b 043 b 042 b 041 b 040 001001 101 0100 00100 b 055 b 054 b 053 b 052 b 051 b 050 001011 102 0101 00101 b 065 b 064 b 063 b 062 b 061 b 060 001101 103 0110 00110 b 075 b 074 b 073 b 072 b 071 b 070 001111 104 0111 00111 b 085 b 084 b 083 b 082 b 081 b 080 010001 105 1000 01000 b 095 b 094 b 093 b 092 b 091 b 090 010011 106 1001 01001 b 105 b 104 b 103 b 102 b 101 b 100 010101 107 1010 01010 b 115 b 114 b 113 b 112 b 111 b 110 010111 108 1011 01011 b 125 b 124 b 123 b 122 b 121 b 120 011001 109 1100 01100 b 135 b 134 b 133 b 132 b 131 b 130 011011 110 1101 01101 b 145 b 144 b 143 b 142 b 141 b 140 011101 111 1110 01110 b 155 b 154 b 153 b 152 b 151 b 150 011111 112 1111 01111 b 165 b 164 b 163 b 162 b 161 b 160 100001 113 10000 b 175 b 174 b 173 b 172 b 171 b 170 100011 114 10001 b 185 b 184 b 183 b 182 b 181 b 180 100101 115 10010 b 195 b 194 b 193 b 192 b 191 b 190 100111 116 10011 b 205 b 204 b 203 b 202 b 201 b 200 101001 117 10100 b 215 b 214 b 213 b 212 b 211 b 210 101011 118 10101 b 225 b 224 b 223 b 222 b 221 b 220 101101 119 10110 b 235 b 234 b 233 b 232 b 231 b 230 101111 120 10111 b 245 b 244 b 243 b 242 b 241 b 240 110001 121 11000 b 255 b 254 b 253 b 252 b 251 b 250 110011 122 11001 b 265 b 264 b 263 b 262 b 261 b 260 110101 123 11010 b 275 b 274 b 273 b 272 b 271 b 270 110111 124 11011 b 285 b 284 b 283 b 282 b 281 b 280 111001 125 11100 b 295 b 294 b 293 b 292 b 291 b 290 111011 126 11101 b 305 b 304 b 303 b 302 b 301 b 300 111101 127 11110 blue b 315 b 314 b 313 b 312 b 311 b 310 111111 128 not used 11111
ST7787 v1.7 2008.04.18 101 9.19 sleep out-command and self-diagnostic functions of the display module 9.19.1 register loading detection sleep out-command (see section 10.1.12 sleep out ( 11h)) is a trigger for an internal function of the display module, which indicates, if the display module loading func tion of factory default values from e-memory (simil ar device) to registers of the display controller is working properly. there are compared factory values of the e-memory a nd register values of the display controller by the display controller. if those both values (e-memory and register values) ar e same, there is inverted (=increased by 1) a bit, which is defined in command 10.1.10 read display self-diagnostic resul t (0fh) (=rddsdr) (the used bit of this command i s d7). if those both values are not same, this bit (d7) is not inve rted (= increased by 1). the flow chart for this internal function is follow ing: note: there is not compared and loaded register val ues, which can be changed by user (00h to afh and dah to ddh), by the display module. sleep in (10h) sleep out mode sleep in mode sleep out (11h) compares e-memory and register values are e-memory and register values same ? d7 inverted no yes rddsdrs d7=0 power on sequence hw reset sw reset loads values from e-memory to registers
ST7787 v1.7 2008.04.18 102 9.20 external light source the operation of the module can meet customers env ironmental reliability requirements. 9.21 oscillator the chip has on-chip oscillator that does not requi re external components. this oscillator output sign al is used for system clock generation for internal display operation. 9.22 system clock generator the timing generator produces the various signals t o driver the internal circuitty. internal chip oper ation is not affected by operations on the data bus. 9.23 instruction decoder and register the instruction decoder indentifies command words a rriving at the interface and routes the following d ata bytes to their destination. the command set can be found in comm and section. 9.24 source driver the source driver block includes 240x3 source outpu ts (s1 to s720), which should be connected directly to the tft-lcd. the source output signals are generated in the data processing block after the data is read out of the ram and latched, which represent the simulatance selected rows. 9.25 gate driver the gate driver block include 320 chanel gate outpu t (g1 to g320) which should be connected directly t o the tft-lcd. 9.25.1 gate driver 9.25.1.1 normal mode s 1 - s3 96 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 1 fi g. 9 . 2 5 .1 g a te dr iv er o u tp u t opt ion 1 2 3 4 5 6 7 8 9 10 11 12 vgh vgl
ST7787 ver. 1.7 2008.04.18 103 10. command 10.1 system function command list and description table 10.1.1 system function command list (1) instruction refer d/cx wrx rdx d17- 8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function nop 10.1.1 0 - 1 - 0 0 0 0 0 0 0 0 (00h) no operation swreset 10.1.2 0 1 - 0 0 0 0 0 0 0 1 (01h) software reset 0 1 - 0 0 0 0 0 1 0 0 (04h) read display id 1 1 - --- --- --- --- --- --- --- --- dummy read 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 id1 read 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 id2 read rddid 10.1.3 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 id3 read 0 - 1 - 0 0 0 0 1 0 0 1 (09h) read display status 1 1 - --- --- --- --- --- --- --- --- dummy read 1 1 - bston my mx mv ml rgb mh st24 - 1 1 - st23 ifpf2 ifpf1 ifpf0 idmon ptlon slout noron - 1 1 - vsson st14 invon st12 st11 dison teon gcs2 - rddst 10.1.4 1 1 - - gcs1 gcs0 telom hson vson pckon deon st0 - 0 - 1 - 0 0 0 0 1 0 1 0 (0ah) read display power mode 1 1 - - --- --- --- --- --- --- --- --- dummy read rddpm 10.1.5 1 1 - - bston idmon ptlon slpout noron dison d1 d0 - 0 - 1 - 0 0 0 0 1 0 1 1 (0bh read display madctl 1 1 - - --- --- --- --- --- --- --- --- dummy read rdd madctl 10.1.6 1 1 - - mx my mv ml rgb mh d1 d0 00h - 0 - 1 - 0 0 0 0 1 1 0 0 (0ch) read display pixel format 1 1 - - --- --- --- --- --- --- --- --- dummy read rdd colmod 10.1.7 1 1 - - vipf3 vipf2 vipf1 vipf0 d3 ifpf2 ifpf1 ifpf0 - 0 - 1 - 0 0 0 0 1 1 0 1 (0dh) read display image mode 1 1 - - --- --- --- --- --- --- --- --- dummy read rddim 10.1.8 1 1 - - vsson d6 invon d4 d3 gcs2 gcs1 gcs0 - 0 - 1 - 0 0 0 0 1 1 1 0 (0eh) read display signal mode 1 1 - - --- --- --- --- --- --- --- --- dummy read rddsm 10.1.9 1 1 - - teon telom hson vson pckon deon d1 d0 00h - 0 - 1 - 0 0 0 0 1 1 1 1 (0fh) read display self-diagnostic result 1 1 - - --- --- --- --- --- --- --- --- dummy read rddsdr 10.1.10 1 1 - - reld fund attd brd d3 d2 d1 d0 - -: dont care
ST7787 ver. 1.7 2008.04.18 104 table 10.1.2 system function command list (2) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function slpin 10.1.11 0 1 - 0 0 0 1 0 0 0 0 (10h) sleep in & booster off slpout 10.1.12 0 1 - 0 0 0 1 0 0 0 1 (11h) sleep out & booster on ptlon 10.1.13 0 1 - 0 0 0 1 0 0 1 0 (12h) partial mode on noron 10.1.14 0 1 - 0 0 0 1 0 0 1 1 (13h) partial mode off normal mode invoff 10.1.15 0 1 - 0 0 1 0 0 0 0 0 (20h) display inversion off normal invon 10.1.16 0 1 - 0 0 1 0 0 0 0 1 (21h) display inversion on 0 1 - 0 0 1 0 0 1 1 0 (26h) gamma curve select gamset 10.1.17 1 1 - gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 - dispoff 10.1.18 0 1 - 0 0 1 0 1 0 0 0 (28h) display off dispon 10.1.19 0 1 - 0 0 1 0 1 0 0 1 (29h) display on 0 1 - 0 0 1 0 1 0 1 0 (2ah) column address set 1 1 - --- --- --- --- --- --- --- xs8 1 1 - xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 00h xaddress start: 0 Q xs Q ef mv=0 1 1 - --- --- --- --- --- --- --- xe8 caset 10.1.20 1 - 1 - xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 afh xaddress end: xs Q xe Q ef mv=0 0 1 - 0 0 1 0 1 0 1 1 (2bh) row address set 1 1 - --- --- --- --- --- --- --- ys8 1 - 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 00h xaddress start: 0 Q ys Q 13f mv=0 1 1 - --- --- --- --- --- --- --- ye8 raset 10.1.21 1 - 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 dbh xaddress end: ys Q ye Q 13f mv=0 0 1 - 0 0 1 0 1 1 0 0 (2ch) memory write ramwr 10.1.22 1 1 - write data * bit asignment varies with the selected interface write data 0 1 - 0 0 1 0 1 1 1 0 (2eh) memory read 1 1 - - --- --- --- --- --- --- --- --- dummy read ramrd 10.1.23 1 1 - - read data * bit asignment varies with the selected interface read data -: dont care
ST7787 ver. 1.7 2008.04.18 105 table 10.1.3 system function command list (3) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 0 0 1 1 0 0 0 0 (30h) partial start/end address set 1 1 - --- --- --- --- --- --- --- psl8 00h 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 00h partial start address 0,1,2,.,219 1 1 - --- --- --- --- --- --- --- pel8 00h ptlar 10.1.25 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 f0h partial end address 0,1,2,.,219 0 1 - 0 0 1 1 0 0 1 1 (33h) scroll area set 1 1 - --- --- --- --- --- --- --- tfa8 1 1 - tfa7 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 top fixed area 0,1,2,.,219 1 1 - --- --- --- --- --- --- --- vsa8 1 1 - vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vertical scroll area 0,1,2,.,219 1 1 - --- --- --- --- --- --- --- bfa8 scrlar 10.1.26 1 1 - bfa7 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 bottom fixed area 0,1,2,.,219 teoff 10.1.27 0 1 - 0 0 1 1 0 1 0 0 (34h) tearing effect line off 0 1 - 0 0 1 1 0 1 0 1 (35h) tearing effect mode set & on teon 10.1.28 1 1 - --- --- --- --- --- --- --- m m="0": mode 1, m="1": mode 2 0 1 - 0 0 1 1 0 1 1 0 (36h) memory data access control madctl 10.1.29 1 1 - my mx mv ml rgb mh --- --- soft rst 0 1 - 0 0 1 1 0 1 1 1 (37h) scroll start address of ram 1 1 - --- --- --- --- --- --- --- ssa8 ssa=0,1,2,.,319 vscsad 10.1.30 1 1 - ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 00h idmoff 10.1.31 0 1 - 0 0 1 1 1 0 0 0 (38h) idle mode off idmon 10.1.32 0 1 - 0 0 1 1 1 0 0 1 (39h) idle mode on 0 1 - 0 0 1 1 1 0 1 0 (3ah) interface pixel format colmod 10.1.33 1 1 - vipf3 vipf2 vipf1 vipf0 --- ifpf2 ifpf1 ifpf0 soft rst 0 1 - 0 0 1 1 1 1 1 1 (3fh) 1 1 - 1 1 0 0 1 0 1 0 cah otp_process 10.1.34 1 1 - 0 0 0 0 0 0 ini 0 otp-process 0 1 - 1 1 0 1 1 0 1 0 (dah) read id1 1 1 - --- --- --- --- --- --- --- --- dummy read rdid1 10.1.35 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 read parameter 0 1 - 1 1 0 1 1 0 1 1 (dbh) read id2 1 1 - --- --- --- --- --- --- --- --- dummy read rdid2 10.1.36 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 read parameter 0 1 - 1 1 0 1 1 1 0 0 (dch) read id3 1 1 - --- --- --- --- --- --- --- --- dummy read rdid3 10.1.37 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 read parameter -: dont care note 1. after the h/w reset by resx pin or s/w rese t by swreset command, each internal register become s default state (refer reset table section) note 2. undefined commands are treated as nop (00 h ) command. note 3. b0 to d9 and de to ff are for factory use o f driver supplier. note 4. commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ml parameter only), 37h, 38h and 39h are updat ed during v-sync when module is in sleep out mode t o avoid abnormal visual effects. during sleep in mode, these command s are updated immediately. read status (09h), read display power mode (0ah), read display madctl (0bh), read display pixe l format (0ch), read display image mode (0dh), read display signal mode (0eh and read display self diagnostic result ( 0fh) of these commands are updated immediately both in sleep in mode and sleep out mode.
ST7787 ver. 1.7 2008.04.18 106 10.2 panel function command list and description table 10.2.1 panel function command list (2) instruction refer d/cx wrx rdx d23-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 0 1 1 0 0 0 0 (b0h) set display i/f mode - --- --- --- icm dp ep hsp vsp rgbctr 10.2.1 1 1 - 0 0 0 0 0 0 0 0 polarity set 0 1 - 1 0 1 1 0 0 0 1 (b1h) in normal mode full colors - --- rtna[6] rtna[5] rtna[4] rtna[3] rtna[2] rtna[1] rtna[0] 1 1 - 0 0 1 1 0 1 1 0 - --- --- --- fpa[4] fpa[3] fpa[2] fpa[1] fpa[0] 1 1 - 0 0 0 0 0 0 1 0 - --- --- --- bpa[4] bpa[3] bpa[2] bpa[1] bpa[0] frmctr1 10.2.2 1 1 - 0 0 0 0 0 0 1 0 blanking porch setting 0 1 - 1 0 1 1 0 0 1 0 (b2h) in idle mode 8-colors - --- rtnb[6] rtnb[5] rtnb[4] rtnb[3] rtnb[2] rtnb[1] rtnb[0] 1 1 - 0 0 1 1 0 1 0 0 - --- --- --- fpb[4] fpb[3] fpb[2] fpb[1] fpb[0] 1 1 - 0 0 0 1 0 0 0 0 - --- --- --- bpb[4] bpb[3] bpb[2] bpb[1] bpb[0] frmctr2 10.2.3 1 1 - 0 0 0 1 0 0 0 0 blanking porch setting 0 1 - 1 0 1 1 0 0 1 1 (b3h) in partial mode + full colors - --- rtnc[6] rtnc[5] rtnc[4] rtnc[3] rtnc[2] rtnc[1] rtnc[0] 1 1 - 0 0 1 1 0 1 1 0 - --- --- --- fpc[4] fpc[3] fpc[2] fpc[1] fpc[0] 1 1 - 0 0 0 1 0 0 0 0 - --- --- --- bpc[4] bpc[3] bpc[2] bpc[1] bpc[0] 1 1 0 0 0 1 0 0 0 0 blanking porch setting line inversion --- rtnd[6] rtnd[5] rtnd[4] rtnd[3] rtnd[2] rtnd[1] rtnd[0] 1 1 0 0 1 1 1 0 0 0 --- --- --- fpd[4] fpd[3] fpd[2] fpd[1] fpd[0] 1 1 0 0 0 1 0 0 0 0 - --- --- --- bpd[4] bpd[3] bpd[2] bpd[1] bpd[0] frmctr3 10.2.4 1 1 0 0 0 1 0 0 0 0 blanking porch setting frame inversion 0 1 - 1 0 1 1 0 1 0 0 (b4h) - --- --- --- --- --- nla nlb nlc invctr 10.2.5 1 1 - 0 0 0 0 0 0 1 0 display inversion control 0 1 - 1 0 1 1 0 1 0 1 (b5h) - --- --- --- --- vfp[3] vfp[2] vfp[1] vfp[0] 1 1 - 0 0 0 0 0 0 0 0 - --- --- --- --- vbp[3] vbp[2] vbp[1] vbp[0] 1 1 - 0 0 0 0 0 0 1 0 - --- --- --- --- hfp[3] hfp[2] hfp[1] hfp[0] 1 1 0 0 0 0 1 0 0 1 --- --- --- --- hbp[3] hbp[2] hbp[1] hbp[0] rgb prctr 10.2.6 1 1 0 0 0 0 1 0 0 1 rgb i/f blanking porch setting 0 1 - 1 0 1 1 0 1 1 0 (b6h) display function setting - --- --- no1 no0 sdt1 sdt0 eq1 eq0 1 1 - 0 0 0 0 0 0 1 0 --- --- --- --- ptg1 ptg0 pt1 pt0 disset5 10.2.7 1 1 0 0 0 0 0 0 1 0 vsyncout 10.2.8 0 1 - 1 0 1 1 1 1 0 0 (bch) external vsync disable vsyncoin 10.2.9 0 1 - 1 0 1 1 1 1 0 1 (bdh) external vsync enable
ST7787 ver. 1.7 2008.04.18 107 table 10.2.2 panel function command list (2) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 -- 1 1 0 0 0 0 0 0 (c0h) -- -- -- -- vrh4 vrh3 vrh2 vrh1 vrh0 pwctr1 10.2.10 1 1 -- 0 0 0 1 0 0 0 0 power control setting 0 1 -- 1 1 0 0 0 0 0 1 (c1h) -- vgh3 vgh2 vgh1 vgh0 vgl3 vgl2 vgl1 vgl0 1 1 -- 1 0 1 1 1 0 0 0 bbh -- -- -- -- -- -- got2 got1 got0 pwctr2 10.2.11 1 1 -- 0 0 0 0 0 0 0 0 power control setting 0 1 -- 1 1 0 0 0 0 1 0 (c2h) -- -- -- -- -- -- apa2 apa1 apa0 1 1 -- 0 0 0 0 0 0` 0 1 - step1a_ sel3 step1a _sel2 step1a _sel1 step1a _sel0 --- step2a _sel2 step2a _sel1 step2a _sel0 1 1 -- 1 0 1 1 0 0 0 1 -- 1 ldo5 _sel2 ldo5 _sel1 ldo5 _sel0 --- step4a _sel2 step4a _sel1 step4a _sel0 1 1 -- 0 0 0 1 0 0 1 1 -- -- step1ap _sel2 step1ap _sel1 step1ap_ sel0 --- step2ap _sel2 step2ap _sel1 step2ap _sel0 1 1 -- 0 0 0 0 0 0 0 0 -- -- -- -- -- -- step4ap _sel2 step4ap _sel1 step4ap _sel0 pwctr3 10.2.12 1 1 -- -- -- -- -- -- 0 0 0 in normal mode full color 0 1 - 1 1 0 0 0 0 1 1 (c3h) -- -- -- -- -- -- apb2 apb1 apb0 1 1 -- 0 0 0 0 0 0 0 1 -- step1b _sel3 step1b _sel2 step1b _sel1 step1b _sel0 --- step2a _sel2 step2a _sel1 step2b _sel0 pwctr4 10.2.13 1 1 -- 0 0 0 0 0 0 0 0 -- -- -- -- -- -- step4b _sel2 step4b _sel1 step4b _sel0 1 1 -- -- -- -- -- -- 0 0 0 step1bp _sel2 step1bp _sel1 step1ap _sel0 -- step2bp _sel2 step2bp _sel1 step2bp _sel0 1 1 -- -- 0 0 0 -- 0 0 0 -- -- -- -- -- -- step4bp _sel2 step4bp _sel1 step4bp _sel0 in idle mode (8-colors) 1 1 -- -- -- -- -- -- 0 0 0 0 1 - 1 1 0 0 0 1 0 0 (c4h) -- -- -- -- -- -- apc2 apc1 apc0 1 1 -- 0 0 0 0 0 0 0 1 - step1c _sel3 step1c _sel2 step1c _sel1 step1c _sel0 --- step2c _sel2 step2c _sel1 step2c _sel0 pwctr5 10.2.14 1 1 -- 1 0 1 1 0 0 1 1 in partial mode + full colors -- -- -- -- -- -- step4c _sel2 step4c _sel1 step4c _sel0 1 1 -- -- -- -- -- -- 0 1 1 -- -- step1cp _sel2 step1cp _sel1 step1cp _sel0 --- step2cp _sel2 step2cp _sel1 step2cp _sel0 1 1 -- -- 0 0 0 -- 0 0 0 -- -- -- -- -- -- step4cp _sel2 step4cp _sel1 step4cp _sel0 1 1 -- -- -- -- -- -- 0 0 0 0 1 - 1 0 1 1 0 1 0 1 (c5h) -- -- vmh6 vmh 5 vmh4 vmh3 vmh2 vmh1 vmh0 1 1 -- -- 0 1 0 1 0 0 0 -- -- vmh_ color8m6 vmh_ color8m5 vmh_ color8m4 vmh_ color8m3 vmh_ color8m2 vmh_ color8m1 vmh_ color8m0 1 1 -- -- 0 1 0 1 0 0 0 -- -- nvm0 --- --- -- --- --- --- vmctr1 10.2.15 -- -- 0 -- -- -- -- -- -- vcom control 1 0 1 -- 1 0 1 1 0 1 1 0 (c6h) -- 0 0 vma5 vma4 vma3 vma2 vma1 vma0 1 1 -- 0 0 0 1 0 1 1 0 -- -- -- vma _idmon05 vma _idmon04 vma _idmon03 vma _idmon02 vma _idmon01 vma _idmon00 vmctr2 10.2.16 1 1 -- -- -- 0 0 0 0 0 0 vcom control 2 -: dont care note 1: c0h to cfh are fixed for about power contro ller. note 2: the c9h to cfh are reserved for further usi ng.
ST7787 ver. 1.7 2008.04.18 108 table 10.2.3 panel function command list (3) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 0 1 0 0 0 0 (d0h) reserved for future using - id17 id16 id15 id14 id13 id12 id11 id10 wrid1 10.2.17 1 1 - 0 0 0 0 0 0 0 0 0 1 - 1 1 0 1 0 0 0 1 (d1h) lcm version code - 0 id26 id25 id24 id23 id22 id21 id20 wrid2 10.2.18 1 1 - 0 1 0 1 1 1 0 0 otp id2 set the lcm version code. 0 1 - 1 1 0 1 0 0 1 0 (d2h) customer project code - id37 id36 id35 id34 id33 id32 id31 id30 wrid3 10.2.19 1 1 - 0 0 0 0 0 0 0 0 otp id3 set the project code. 0 1 - 1 1 0 1 1 1 1 0 deh otp-read command otp-load 10.2.20 1 1 - 0 1 1 1 0 1 0 1 75h 0 1 - 1 1 0 1 1 1 1 0 dfh 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 otp-prog 10.2.21 1 1 0 1 0 1 1 0 1 0 cah 00h aah a5h 5ah otp prog. command protection sequence:ca 00aa a5 a5 5a -: dont care note 1: the d1h to d8h registers are fixed for abou t id code setting. note 2: the d9h, deh and dfh registers are used for nv memory function controller. (ex: write, clear, etc.)
ST7787 ver. 1.7 2008.04.18 109 table 10.2.4 panel function command list (4) instruction refer d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 1 0 0 0 0 0 (e0h) set gamma correction - mva_en --- --- --- rfp0[3] rfp0[2] rfp0[1] r fp0[0] 1 1 - 0 0 0 0 0 0 0 1 --- --- --- --- pkp0[3] pkp0[2] pkp0[1] pkp0[0] 1 1 0 0 0 0 1 1 0 0 --- --- --- pkp1[4] pkp1[3] pkp1[2] pkp1[1] pkp1[0] 1 1 0 0 0 1 1 0 0 1 --- --- --- pkp2[4] pkp2[3] pkp2[2] pkp2[1] pkp2[0] 1 1 0 0 0 1 1 1 0 0 --- --- --- pkp3[4] pkp3[3] pkp3[2] pkp3[1] pkp3[0] 1 1 0 0 0 1 1 0 1 1 --- --- --- pkp4[4] pkp4[3] pkp4[2] pkp4[1] pkp4[0] 1 1 0 0 0 1 1 0 0 1 --- --- --- pkp5[4] pkp5[3] pkp5[2] pkp5[1] pkp5[0] 1 1 0 0 0 1 1 0 0 0 --- --- --- pkp6[4] pkp6[3] pkp6[2] pkp6[1] pkp6[0] 1 1 0 0 0 1 1 0 1 0 --- --- --- pkp7[4] pkp7[3] pkp7[2] pkp7[1] pkp7[0] 1 1 0 0 0 0 1 1 0 1 --- --- --- --- pkp8[3] pkp8[2] pkp8[1] pkp8[0] 1 1 0 0 0 0 0 0 0 1 --- --- --- --- rfp1[3] rfp1[2] rfp1[1] rfp1[0] 1 1 0 0 0 0 0 0 1 0 --- --- --- --- 0 osp1[2] osp1[1] osp1[0] gamctrp1 10.2.22 1 1 - 0 0 0 0 0 0 1 1 postiive polarity 0 1 - 1 1 1 0 0 0 0 1 (e1h) set gamma correction - --- --- --- --- rfn0[3] rfn0[2] rfn0[1] rfn0[0] 1 1 - 0 0 0 0 0 0 0 1 --- --- --- --- pkn0[3] pkn0[2] pkn0[1] pkn0[0] 1 1 0 0 0 0 1 1 0 0 --- --- --- pkn1[4] pkn1[3] pkn1[2] pkn1[1] pkn1[0] 1 1 0 0 0 1 1 0 0 1 --- --- --- pkn2[4] pkn2[3] pkn2[2] pkn2[1] pkn2[0] 1 1 0 0 0 1 1 1 0 0 --- --- --- pkn3[4] pkn3[3] pkn3[2] pkn3[1] pkn3[0] 1 1 0 0 0 1 1 0 1 1 --- --- --- pkn4[4] pkn4[3] pkn4[2] pkn4[1] pkn4[0] 1 1 0 0 0 1 1 0 0 1 --- --- --- pkn5[4] pkn5[3] pkn5[2] pkn5[1] pkn5[0] 1 1 0 0 0 1 1 0 0 0 --- --- --- pkn6[4] pkn6[3] pkn6[2] pkn6[1] pkn6[0] 1 1 0 0 0 1 1 0 1 0 --- --- --- pkn7[4] pkn7[3] pkn7[2] pkn7[1] pkn7[0] 1 1 0 0 0 0 1 1 0 1 --- --- --- --- pkn8[3] pkn8[2] pkn8[1] pkn8[0] 1 1 0 0 0 0 0 0 0 1 --- --- --- --- rfn1[3] rfn1[2] rfn1[1] rfn1[0] 1 1 0 0 0 0 0 0 1 0 1 1 --- --- --- --- --- osn1[2] osn1[1] osn1[0] gamctrn1 10.2.23 - 0 0 0 0 0 0 1 1 negative polarity 0 1 - 1 1 1 1 0 1 0 0 (fbh) vcom multi mode -- 1 vcom _ mu_mode 1 1 1 1 1 vcom_multi_mode10.2.24 1 1 - 1 1 1 1 1 1 1 -: dont care note 1: e0-e7 registers are fixed for about gamma a djusting.
ST7787 ver. 1.7 2008.04.18 110 10.1.1 nop (00h) 00h nop (no operation) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) nop 0 1 - 0 0 0 0 0 0 0 0 (00h) parameter no parameter - note: - dont care description -this command is empty command. it does not have ef fect on the display module. -however it can be used to terminate ram data write or read as described in ramwr (memory write), ramrd (memory read) and parameter write commands. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart -
ST7787 ver. 1.7 2008.04.18 111 10.1.2 swreset (01h): software reset 01h swreset (software reset) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) swreset 0 1 - 0 0 0 0 0 0 0 1 (01h) parameter no parameter - note: - dont care description -when the software reset command is written, it cau ses a software reset. it resets the commands and parameters to their s/w reset default values and al l source & gate outputs are set to vss (display off ). (see default tables in each command description) note: the frame memory contents are not affected by this command. restriction -it will be necessary to wait 120msec before sendin g new command following software reset. -the display module loads all display supplier s f actory default values to the registers during 120ms ec. -if software reset is applied during sleep out mode , it will be necessary to wait 120msec before sending sleep out command. -software reset command cannot be sent during sleep out sequence. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart swrese t (01 h) l e ge nd display whole blank screen set commands to s/w default value co mm a n d parameter display action m o d e s le ep in m o d e sequential
ST7787 ver. 1.7 2008.04.18 112 10.1.3 rddid (04h): read display id 04h rddid (read display id) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddid 0 1 - 0 0 0 0 0 1 0 0 (04h) 1 st parameter 1 1 - - - - - - - - - dummy 2 nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 3 rt parameter 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 4 th parameter 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 note: - dont care description -this read byte returns 24-bit display identificati on information. -the 1st parameter is dummy data -the 2nd parameter (id17 to id10): lcd modules man ufacturer id. -the 3rd parameter (id27 to id20): lcd module/drive r version id -the 4th parameter (id37 to ud30): lcd module/drive r id. note: commands rdid1/2/3(dah, dbh, dch) read data c orrespond to the parameters 2,3,4 of the command 04 h, respectively. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status id1 id2 id3 power on sequence n/a n/a n/a s/w reset n/a n/a n/a h/w reset n/a n/a n/a flow chart s e rial i/f m od e p a rall e l i/f mo d e rdd i d (0 4h) d u m my c l ock rddid ( 0 4 h) d umm y r ead host dr iver s e nd id1[7:0] s e nd id1[7:0] s e nd id2[7:0] s e nd id3[7:0] s e nd id2[7:0] s e nd id3[7: 0] leg en d command parameter d i s p lay a ct i on m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 113 10.1.4 rddst (09h): read display status 09h rddst (read display status) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddst 0 1 - 0 0 0 0 1 0 0 1 (09h) 1st parameter 1 1 - - - - - - - - - - 2nd parameter 1 1 - bston my mx mv ml rgb mh st24 3rd parameter 1 1 - st23 ifpf2 ifpf1 ifpf0 idmon ptlon slout noron 4th parameter 1 1 - vsson st14 invon st12 st11 dison teon gcs2 5th parameter 1 1 gcs1 gcs0 telom hson vson pckon deon st0 note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description value bston booster voltage status 1 =booster on, 0 =booster off my row address order (my) 1 =decrement, (bottom to top, when madctl (36h) d 7=1) 0 =increment, (top to bottom, when madctl (36h) d 7=0) mx column address order (mx) 1 =decrement, (right to left, when madctl (36h) d 6=1) 0 =increment, (left to right, when madctl (36h) d 6=1) mv row/column exchange (mv) 1 = row/column exchange, (when madctl (36h) d5=1 ) 0 = normal, (when madctl (36h) d5=0) ml scan address order (ml) 1 =decrement, (lcd refresh top to bottom, when madctl (36h) d4=1 ) 0=increment, (lcd refresh bottom to top, when madctl (36h) d4=0 ) rgb rgb/ bgr order (rgb) 1 =bgr, (when madctl (36h) d3=1) 0 =rgb, (when madctl (36h) d3=0) mh horizontal order 1 =decrement, (lcd refresh left to right, when madctl (36h) d2=1 ) 0 =increment, (lcd refresh right to left, when madctl (36h) d2=0 ) st24 for future use 0 st23 for future use 0 ifpf2 ifpf1 ifcpf0 interface color pixel format definition 011 = 12-bit / pixel, 101 = 16-bit / pixel, 110 = 18-bit / pixel, others are no define idmon idle mode on/off 1 = on, 0 = off ptlon partial mode on/off 1 = on, 0 = off slpout sleep in/out 1 = out, 0 = in noron display normal mode on/off 1 = normal display, 0 = partial display vsson vertical scrolling status 1 = scroll on,0 = scroll off st14 horizontal scroll status 0 invon inversion status 1 = on, 0 = off st12 all pixels on (not used) 0 st11 all pixels off (not used) 0 dison display on/off 1 = on, 0 = off teon tearing effect line on/off 1 = on, 0 = off telom tearing effect line mode 0 = mode1, 1 = m ode2 hson horizontal sync. (hs, rgb i/f) 1 = on, 0 = off vson vertical sync, (vs, rgb i/f) 1 = on, 0 = o ff pclkon pixel clock (pclk, rgb i/f) 1 = on, 0 = off deon data enable (de, rgb i/f) 1 = on, 0 = off st0 for future use 0 gs gc[7:0] gcs[2:0] tr lctype 01h 000 =1.0 02h 001 =2.5 04h 010 (lcm=[01]) =2.2 0 08h 011 =1.8 01h 000 (lcm=[01]) =2.2 02h 001 =1.8 1 04h 010 =2.5
ST7787 ver. 1.7 2008.04.18 114 note: st0, st5, st9, st11-st15, st19, st23, st24 ar e set to 0, when rgb i/f. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (st31 to st0) st[31-24] st[23-16] st[15-8] st[7-0] power on sequence 0000-0000 0110-0001 0000-0000 0000-0000 s/w reset 0xxx0xx00 0xxx-0001 0000-0000 0000-0000 h/w reset 0000-0000 0110-0001 0000-0000 0000-0000 flow chart serial i/f m o de p a rall e l i/f mod e rddst (0 9h) d u m my c lo ck rdds t (09 h) d umm y r ead h o st dr i v er s e nd s t [31:24] s e nd s t [23:16] s e nd st[31: 2 4] s e nd st[23: 1 6] s e nd st[15: 8] s e nd s t [7:0] s e nd s t [15:8] s e nd st[7: 0] leg en d command parameter d i s p lay a ct i on m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 115 10.1.5 rddpm (0ah): read display power mode 0ah rddpm (read display power mode) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddpm 0 1 - 0 0 0 0 1 0 1 0 (0ah) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 bston idmon ptlon slpout noron dison d1 d0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: bit description value bston booster voltage status 1 =booster on, 0 =booster off idmon idle mode on/off 1 = idle mode on, 0 = idle mode off ptlon partial mode on/off 1 = partial mode on, 0 = partial mode off slpon sleep in/out 1 = sleep out, 0 = sleep in noron display normal mode on/off 1 = normal display, 0 = partial display dison display on/off 1 = display on, 0 = display off d1 not used 0 d0 not used 0 restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 08h s/w reset 08h h/w reset 08h flow chart s e ri a l i/f mod e rddpm (0ah) s e nd d [7:0] parall e l i/f mo d e rddpm (0ah) d umm y r ead host dr iv er l e ge nd command parameter display a ct ion s en d d [7:0] m od e sequential transfer
ST7787 ver. 1.7 2008.04.18 116 10.1.6 rddmadctl (0bh): read display madctl 0bh rddmadctl (read display madctl) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddmadctl 0 1 - 0 0 0 0 1 0 1 1 (0bh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 my mx mv ml rgb mh d1 d0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: bit description value mx row address order 1 = bottom to top (when madctl b7=1) 0 = top to bottom (when madctl b7=0) my column address order 1 = right to left (when madctl b6=1) 0 = left to right (when madctl b6=0) mv row/column order (mv) 1 = row/column exchange (mv=1) 0 = normal (mv=0) ml vertical refresh order 1 =lcd refresh bottom to top 0 =lcd refresh top to bottom rgb rgb/bgr order 1 =bgr, 0=rgb mh horizontal order 1 =lcd refresh right to left 0 =lcd refresh left to right d1 not used 0 d0 not used 0 restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 00h s/w reset no change h/w reset 00h flow chart s e rial i/f m o d e rddmadctl (0bh) s e nd d[7: 0] p a rallel i/f mod e rddmadctl (0bh) d umm y r ead h o st dr i v er leg en d command parameter display a ct i on s e nd d[7:0] m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 117 10.1.7 rddcolmod (0ch): read display pixel format 0ch rddcolmod (read display pixel format) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddcolmod 0 1 - 0 0 0 0 1 1 0 0 (0ch) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - vipf3 vipf2 vipf1 vipf0 d3 ifpf2 ifpf1 ifpf0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: ifpf[2:0] mcu interface color format 011 3 12-bit/pixel 101 5 16-bit/pixel 110 6 18-bit/pixel 111 7 no used others are no define and invalid vifpf[2:0] rgb interface color format 0101 5 16-bit/pixel (1-times data transfer) 0110 6 18-bit/pixel (1-times data transfer) 0111 7 no used 1110 14 18-bit/pixel (3-times data transfer) others are no define and invalid restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value ifpf[2:0] vipf[3:0] power on sequence 0110 (18 bits/pixel) 0110 (18 bit s/pixel) s/w reset no change no change h/w reset 0110 (18 bits/pixel) 0110 (18 bits/pixel) flow chart s e rial i/f m o d e rddcolmod (0ch) s e nd d[7: 0] p a rallel i/f mod e rddcolmod (0ch) d umm y r ead h o st d r i v er leg en d command parameter display a ct i on s e nd d[7:0] m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 118 10.1.8 rddim (0dh): read display image mode 0dh rddim (0dh): read display image mode inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddim 0 1 - 0 0 0 0 1 1 0 1 (0dh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - vsson d6 invon d4 d3 gcs2 gcs1 gcs0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: bit description value vsson vertical scrolling on/off 1 = vertical scrolling is on, 0 = vertical scrolling is off d6 horizontal scrolling on/off 0 (not used) invon inversion on/off 1 = inversion is on, 0 = inversion is off d4 all pixels on 0 (not used) d3 all pixels off 0 (not used) gs gc[7:0] reg. lcm1 lcm0 lc type gamma 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 01h 1 1 n/a curve 2.2 02h x x transflective(tr) 1.8 04h x x transflective(tr) 2.5 1 08h x x transflective(tr) 1.0 01h x x transflective(tr) 1.0 02h x x transflective(tr) 2.5 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 04h 1 1 n/a curve 2.2 0 08h x x transflective(tr) 1.8 note 1: while lcm[1:0]=00 note 2: even gcs[2:0] value is be changeable from r ead status, the gamma curve of transmissive and mva only =2.2. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value(d7 to d0) power on sequence 0000_0001 (01h) s/w reset 0000_0001 (01h) h/w reset 0000_0001 (01h)
ST7787 ver. 1.7 2008.04.18 119 flow chart s e rial i/f m o d e rddim (0dh) s e nd d[7: 0] p a rallel i/f mod e rddim (0dh) d umm y r ead h o st dr i v er leg en d command parameter display a ct i on s e nd d[7:0] m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 120 10.1.9 rddsm (0eh): read display signal mode 0eh rddsm (0eh): read display signal mode inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddsm 0 1 - 0 0 0 0 1 1 1 0 (0eh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - teon telom hson vson pckon deon d1 d0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: bit description value teon tearing effect line on/off 1 = on, 0 = off telom tearing effect line mode 1 = mode1, 0 = mode2 hson horizontal sync. (rgb i/f) on/off 1 = on, 0 = off vson vertical sync. (rgb i/f) on/off 1 = on, 0 = off pckon pixel clock (pclk, rgb i/f) on/off 1 = on, 0 = off deon data enable (de, rgb i/f) on/off 1 = on, 0 = off d1 not used 1 = on, 0 = off d0 not used 1 = on, 0 = off restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value(d7~d0) power on sequence 00h s/w reset 00h h/w reset 00h flow chart s e rial i/f m o d e rddsm (0eh) s e nd d[7: 0] p a rallel i/f mod e rddsm (0eh) d umm y r ead h o st dr i v er leg en d command parameter display a ct i on s e nd d[7:0] m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 121 10.1.10 rddsdr (0fh): read display self-diagnostic result 0fh rddsdr (0fh): read display self-diagnostic result inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddsdr 0 1 - 0 0 0 0 1 1 1 1 (0fh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - reld fund attd brd d3 d2 d1 d0 note: - dont care, can be set to vddi or dgnd le vel description this command indicates the current status of the di splay as described in the table below: bit description value reld register loading detection see section 9.19 fund functionality detection see section 9.19 attd chip attachment detection 1 brd display glass break detection 1 d3 not used 0 d2 not used 0 d1 not used 0 d0 not used 0 restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value(d7~d0) power on sequence s/w reset h/w reset flow chart s e rial i/f m o d e rddsdr (0fh) s e nd d[7: 0] p a rallel i/f mod e rddsdr (0fh) d um m y r ead h o st dr i v er leg en d command parameter display a ct i on s e nd d[7:0] m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 122 10.1.11 slpin (10h): sleep in 10h slpin (sleep in) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpin 0 1 - 0 0 0 1 0 0 0 0 (10h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command causes the lcd module to enter the mini mum power consumption mode. -in this mode the dc/dc converter is stopped, internal display oscillator is stopped, and panel scanning is stopped. -mcu interface and memory are still working and the m emory keeps its contents restriction -this command has no effect when module is already in sleep in mode. sleep in mode can only be exit by the sleep out command (11h). -it will be necessary to wait 120msec before sending next command , this is to allow tim e for the supply voltages and clock circuits to stabilize. -it will be necessary to wait 120msec after sending sleep out command (when in sleep in m ode) before sleep in command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode sl ee p in v d di 1.6 v - 3.0v v dd gate output source output 0v blanking display (over 1frame display) * v com output 0v 2.6 v - 3.0v stop 0v internal counter stop internal oscillator st o p dc c ha rg e in c a p a c i t o rs disc h arge 0 v o r vdd v gh 0v or vdd vgl 0v avdd 0v or vdd ic internal reset 0v * note: complete 1 frame display (ex: continue 2-falling edges of vs)
ST7787 ver. 1.7 2008.04.18 123 flow chart -it takes about 120msec to get into sleep in mode ( booster off state) after slpin command issued. -the results of booster off can be check by rddst ( 09h) command bit31. s plin (10 h ) display whole blank screen (automatic no effect to disp on/off command) drain charge fr o m l c d s top dc/dc converter stop internal oscillator sleep in l eg en d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 124 10.1.12 slpout (11h): sleep out 11h slpout (sleep out) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpout 0 1 - 0 0 0 1 0 0 0 1 (11h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command turns off sleep mode. -in this mode the dc/dc converter is enabled, inter nal display oscillator is started, and panel scanni ng is started. restriction -this command has no effect when module is already in sleep out mode. sleep out mode can only be exit by the sleep in command (10h). -it will be necessary to wait 120msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -driver loads all default values of extended and te st command to the registers during this 120msec and there cannot be any abnormal visual effect on the d isplay image if those default and register values a re same when this load is done and when the driver is already sleep out mode. -driver is doing self-diagnostic functions during t his 120msec . see also section 9.20. -it will be necessary to wait 120msec after sending sleep in command (when in sleep out m ode) before sleep out command can be sent register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode s l ee p o ut v ddi 1.6 v - 3.0v vdd internal oscillator stop start avdd 0v or vdd vgl 0v vgh 0v or vdd internal counter stop start ic internal reset 0v 2.6 v - 3.0v g a t e output source output v c om output s t op 0v 0v s t op 0v 0v me m ory con t en ts me m ory co n t e n ts b la n k ing di s p la y ( o v e r 1 f r a m e di s p lay ) * if d i s pon 2 9h i s s et * no t e : c o mp le t e 1 fr a me d is pl a y ( ex : c o nt i nue 2 - f a l l ing e dg e s o f vs)
ST7787 ver. 1.7 2008.04.18 125 flow chart -it takes 120msec to become sleep out mode (booster on mode) after s lpout command issued. -the results of booster on can be checked by rddst (09h) command bit31. slpou t ( 1 1 h) start internal oscillator start dc-dc converter charge offset voltage for lcd panel display whole blank screen for 2 frames (automatic no effect to disp on/off display memory contents in accordance with the current command table settings sleep out le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 126 10.1.13 ptlon (12h): partial display mode on 12h ptlon (12h): partial display mode on inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlon 0 1 - 0 0 0 1 0 0 1 0 (12h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command turns on partial mode. the partia l mode window is described by the partial area comm and (30h) -to leave partial mode, the normal display mode on command (13h) should be written. -there is no abnormal visual effect during mode cha nge between normal mode on <-> partial mode on. restriction this command has no effect when partial mode is act ive. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart see partial area (30h)
ST7787 ver. 1.7 2008.04.18 127 10.1.14 noron (13h): normal display mode on 13h noron (normal display mode on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) noron 0 1 - 0 0 0 1 0 0 1 1 (13h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command returns the display to normal mode. -normal display mode on means partial mode off , scroll mode off . -exit from noron by the partial mode on command (12 h) -there is no abnormal visual effect during mode cha nge from normal mode on to partial mode on. restriction -this command has no effect when normal display mod e is active. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart -see partial area and vertical scrolling definition descriptions for details of when to use this comma nd
ST7787 ver. 1.7 2008.04.18 128 9.1.15 invoff (20h): display inversion off 20h ivnoff (normal display mode off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invoff 0 1 - 0 0 1 0 0 0 0 0 (20h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to recover from display inver sion mode. -this command makes no change of contents of frame memory . -this command does not change any other status. restriction -this command has no effect when module is already inversion off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart t op - le f t (0,0) ( e x amp le ) me m o ry d is pl ay d i s pl ay inv ers i o n o n m ode l ege n d command p a r a met er i nvoff (2 0h) d is pl a y ac t i on display inversion off m o d e sequential transfer
ST7787 ver. 1.7 2008.04.18 129 10.1.16 invon (21h): display inversion on 21h ivnoff (display inversion on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invon 0 1 - 0 0 1 0 0 0 0 1 (21h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to enter into display inversi on mode -this command makes no change of contents of frame memory . -this command does not change any other status. -to exit from display inversion on, the display inv ersion off command (20h) should be written. restriction -this command has no effect when module is already inversion on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart d i s pl ay inv ers i o n o n m ode l ege n d command p a r a met er i nvo n (2 1 h) d is pl a y ac t i on display inversion off m o d e sequential transfer t op - le f t (0,0) (e x a mp le ) m e m o ry d is pl ay
ST7787 ver. 1.7 2008.04.18 130 10.1.17 gamset (26h): gamma set 26h gamset (gamma set) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamset 0 1 - 0 0 1 0 0 1 1 0 (26h) 1 st parameter 1 1 - gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 note: - dont care, can be set to vddi or dgnd le vel description -this command is used to select the desired gamma c urve for the current display. a maximum of 4 curves can be selected. the curves are defined in section 9.17 the curve is selected by setting the appropria te bit in the parameter as described in the table. gs gc[7:0] reg. lcm1 lcm0 lc type gamma 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 01h 1 1 n/a curve 2.2 02h x x transflective(tr) 1.8 04h x x transflective(tr) 2.5 1 08h x x transflective(tr) 1.0 01h x x transflective(tr) 1.0 02h x x transflective(tr) 2.5 0 0 mva 0 1 transflective(tr) 1 0 transmissive(tm) 04h 1 1 n/a curve 2.2 0 08h x x transflective(tr) 1.8 note: all other values are undefined. restriction -values of gc [7:0] not shown in table above are in valid and will not change the current selected gamm a curve until valid is received . register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 01h s/w reset 01h h/w reset 01h
ST7787 ver. 1.7 2008.04.18 131 flow chart ---------------- g am set (2 6 h ) l e ge nd com and param e ter 1 st parameter: gc[7:0] d is pl ay action m ode new ga m m a c u r v e l oad e d sequential
ST7787 ver. 1.7 2008.04.18 132 10.1.18 dispoff (28h): display off 28h dispoff (display off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispoff 0 1 - 0 0 1 0 1 0 0 0 (28h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to enter into display off mod e. in this mode, the output from frame memory is disables and blank page inserted. -this command makes no change of contents of frame memory. -this command does not change any other status. -there will be no abnormal visible effect on the di splay. -exit from this command by display on (29h) restriction -this command has no effect when module is already in display off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off t op - le f t (0,0) (e x amp l e) me m o r y d i s p lay v d di d is pl a y o ff 1.6 v - 3.0v v dd gate output source output 0v blanking display (over 1 frame display) * 2.6 v - 3.0v s t o p vcom output 0v 0v internal counter stop i n t e rn a l o s c i l la t o r v g h v gl a v d d ic int e rn a l r e s e t * n o t e : c o mpl e t e 1 f r a m e di s p la y ( ex : c o ntin u e 2 - f al l i ng e dg e s o f v s)
ST7787 ver. 1.7 2008.04.18 133 flow chart d i s pl ay inv ers i o n o n m ode l ege n d command p a r a met er dispoff (2 8 h) d is pl a y ac t i on display inversion off m o d e sequential transfer
ST7787 ver. 1.7 2008.04.18 134 10.1.19 dispon (29h): display on 29h dispon (display on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispon 0 1 - 0 0 1 0 1 0 0 1 (29h) 1 st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to recover from display off m ode. output from the frame memory is enabled. -this command makes no change of contents of frame memory. -this command does not change any other status. restriction -this command has no effect when module is already in display on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off t op - le f t (0,0) (e x amp l e) me m o r y d i s pl ay v d di vdd gate output s o ur c e outp u t di s p la y on blanking display (over 1 frame display) * stop 0v 1.6 v - 3.0v 2.6v-3.0v memory contents vcom output 0v memory contents internal counter stop start int e rn a l o s ci l l a t o r vgh vgl a v dd ic int e r na l r e s e t * no t e : c o m p l e te 1 fr a me d i s pl a y ( ex : c o ntinu e 2 - f a l l ing e dg e s o f v s )
ST7787 ver. 1.7 2008.04.18 135 flow chart d i s pl ay off m ode l ege n d command p a r a met er dispon (2 9 h) d is pl a y ac t i on display on mode m o d e sequential transfer
ST7787 ver. 1.7 2008.04.18 136 10.1.20 caset (2ah): column address set 2ah caset(colume address set)_ inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamset 0 1 - 0 0 1 0 0 1 1 0 (2ah) 1 st parameter 1 1 - - - - - - - - xs8 2 nd parameter 1 1 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 3 rd parameter 1 1 - - - - - - - xe8 4 th parameter 1 1 xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 note: - dont care, can be set to vddi or dgnd le vel description -this command is used to define area of frame memor y where mcu can access. -this command makes no change on the other driver s tatus. -the value of xs [8:0] and xe [8:0] are referred wh en ramwr command comes. -each value represents one column line in the frame memory. restriction xaddress start: 0 Q xs Q ef mv=0 xaddress end: xs Q xe Q ef mv=0 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default 1. 240x320 memory base default value 2 status xs[8:0] xe[8:0] power on sequence 0000h 00efh s/w reset 0000h 00efh h/w reset 0000h 00efh ( e x a m p l e ) x s[ 8 :0] x e[ 8 :0]
ST7787 ver. 1.7 2008.04.18 137 flow chart parti a l mo d e c a set ( 2ah ) 1 s t & 2 n d parameter: xs[8:0] 3 rd & 4 th p a r a meter: x e [ 8 :0] r a set (2b h ) 1 st & 2 nd parameter: ys[8:0] 3 rd & 4 th parameter: ye[8:0] r a m wr (2c h ) l ege n d c o mm an d par a m e t er i mage da t a d 1 [ 17 : 0 ],d2[ 17 :0 ] d n [ 17 :0] d is pl ay ac t i on m o de any co m ma nd sequential
ST7787 ver. 1.7 2008.04.18 138 10.1.21 raset (2bh): row address set 2bh raset (row address set) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) raset (2bh) 0 1 - 0 0 1 0 1 0 1 1 (2bh) 1st parameter 1 1 - - - - - - - - ys8 2nd parameter 1 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 3rd parameter 1 1 - - - - - - - - ye8 4th parameter 1 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 note: - dont care, can be set to vddi or dgnd le vel description this command is used to define area of frame memory where mcu can access. this command makes no change on the other driver st atus. the value of ys [8:0] and ye [8:0] are referred whe n ramwr command comes. each value represents one column line in the frame memory. restriction xaddress start: 0 Q ys Q 13f mv=0 xaddress end: ys Q ye Q 13f mv=0 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default 1. 240x320 memory base default value 2 status ys[8:0] ye[8:0] power on sequence 0000h 013fh s/w reset 0000h 013fh h/w reset 0000h 013fh y s[ 8 :0] y e[ 8 : 0] example
ST7787 ver. 1.7 2008.04.18 139 flow chart parti a l mo d e c a set ( 2ah ) 1 s t & 2 n d parameter: xs[8:0] 3 rd & 4 th parameter: xe[8:0] r a set (2b h ) 1 s t & 2 n d parameter: ys[8:0] 3 rd & 4 th p a r a meter: y e[ 8 :0] r a m w r (2c h ) l ege n d c o mm an d param e t er i mage da t a d 1 [ 17 : 0 ],d2[ 17 :0 ] d n [ 17 :0] d is pl ay ac t i on m o de any co m ma nd sequential
ST7787 ver. 1.7 2008.04.18 140 10.1.22 ramwr (2ch): memory write 2ch ramwr (memory write) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramwr 0 1 - 0 0 1 0 1 1 0 0 (2ch) 1st parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - O 1 1 O O O O O O O O O O nth parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to transfer data from mcu to frame memory. -this command makes no change to the other driver s tatus. -when this command is accepted, the column register and the row register are reset to the start column/start row positions. -the start column/start row positions are different in accordance with madctl setting. (see section 9. 12) -then d[23:0] is stored in frame memory and the col umn register and the row register incremented as section 9.10.2. -sending any other command can stop frame write. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randoml y s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared flow chart r a m w r (2c h ) l ege n d c o mm an d par a m e t er i mage da t a d 1 [ 17 : 0 ],d2[ 17 :0 ] d n [ 17 :0] d is pl ay ac t i on m o de any co m ma nd sequential
ST7787 ver. 1.7 2008.04.18 141 10.1.23 ramrd (2eh): memory read 2eh ramrd (memory read) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramrd 0 1 - 0 0 1 0 1 1 1 0 (2eh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - O 1 1 O O O O O O O O O O (n+1) th parameter 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to transfer data from frame m emory to mcu. -this command makes no change to the other driver s tatus. -when this command is accepted, the column register and the row register are reset to the start column/start row positions. -the start column/start row positions are different in accordance with madctl setting. (see section 9. 12) -then d[23:0] is read back from the frame memory an d the column register and the row register incremented as section 9.10.2. -frame read can be canceled by sending any other co mmand. -see section 9.8 data color coding for color codi ng (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. restriction -in all color modes, the frame read is always 18- b its and there is no restriction on length of parame ters. -memory read is only possible via the spi and paral lel interface register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randoml y s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared flow chart r a mrd ( 2 e h ) l e ge nd d u m m y read image data d1[ 17 :0],d 2 [ 17 : 0 ] d n [ 17 : 0] co mm a nd parameter display action mode a n y c o mm an d sequential
ST7787 ver. 1.7 2008.04.18 142 10.1.24 ptlar (30h): partial area 30h ptlar (partial area) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlar 0 1 - 0 0 1 1 0 0 0 0 (30h) 1 st parameter 1 1 - -- -- -- -- -- -- -- psl8 2 nd parameter 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 3 rd parameter 1 1 - -- -- -- -- -- -- -- pel8 4 th parameter 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 note: - dont care, can be set to vddi or dgnd le vel description -this command defines the partial modes display ar ea. - there are 4 parameters associated with this command , the first defines the start row (psl) and the second the end row (pel), as illustrated in the figures below. psl and pel refer to the frame memory row address counter. -if end row = start row then the partial area will be one row deep. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status psl[8] psl[7:0] pe[8] pel[7:0] power on sequence 0h 0000h 0h 0000h s/w reset 0h 0000h 0h 0000h h/w reset 0h 0000h 0h 0000h - i f e n d row > st art ro w , w h en ma dc t l m l = 0 s t a rt ro w p s l [ 8 :0] n o n - d is pl a y i n g ar ea p a rti a l di s p lay a r ea p e l [ 8 :0] e nd r o w n o n - d i s p l a y ing ar ea - i f e n d row > st art ro w , w h en ma dc t l m l = 1 e nd r o w p e l [ 8 :0] n o n - d is pl a y i n g ar ea p a rti a l di s p lay a r ea p s l [ 8 :0] s t a rt ro w n o n - d i s p l a y ing ar ea - i f e n d row < st art ro w , w h en ma dc t l m l = 0 e n d r o w n o n - di s p lay ing ar ea p a rti a l d i s p la y ar ea p s l [ 8 :0] s t a rt ro w p e l [ 8 :0]
ST7787 ver. 1.7 2008.04.18 143 flow chart 1. t o e n t e r partial m o d e 2. t o e x it p a rtial m od e p t yla r (3 0h ) 1 st & 2 nd parameter: psel[8:0] 3 rd & 4 th paramete r: pel[8:0] ptlon (12h) partial mode d p a rt i al m ode dispoff (28h) noron (13h) partial mode off ramrw (2ch) image data d1[17:0],d2[17:0] dn[17:0] dison (29h) optional to prevent tearing effect image display legend command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 144 10.1.25 scrlar (33h): scroll area 33h scrlar (scrolll area) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlar 0 1 - 0 0 1 1 0 0 1 1 (33h) 1 st parameter 1 1 - --- --- --- --- --- --- --- tfa8 2 nd parameter 1 1 - tfa7 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 3 rd parameter 1 1 - --- --- --- --- --- --- --- vsa8 4 th parameter 1 1 - vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 5 th parameter 1 1 - --- --- --- --- --- --- --- bfa8 6 th parameter 1 1 - bfa7 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 note: - dont care, can be set to vddi or dgnd le vel description -this command defines the vertical scrolling area o f the display. when madctl ml=0 the 1 st & 2 nd parameter tfa [8:0] describes the top fixed area ( in no. of lines from top of the frame memory and display). the 3 rd & 4 th parameter vsa [8:0] describes the height of the ve rtical scrolling area (in no. of lines of the frame memory [not the display] from the vertica l scrolling start address) the first line appears immediately after the bottom most line of the top fixed area. the 5 th & 6 th parameter bfa [8:0] describes the bottom fixed area (in no. of lines from bottom of the frame memory and display). tfa, vsa and bfa refer to the frame memory row addr ess. when madctl ml=1 the 1 st & 2 nd parameter tfa [8:0] describes the top fixed area (i n no. of lines from bottom of the frame memory and display). the 3 rd & 4 th parameter vsa [8:0] describes the height of the ve rtical scrolling area (in no. of lines of the frame memory [not the display] from the vertical scrolling start address) the first line appears immediately after the top mo st line of the top fixed area. the 5 th & 6 th parameter bfa [8:0] describes the bottom fixed area (in no. of lines from top of the frame memory and display). see section 9.10.4 for details of the memory to dis play mapping. restriction -in vertical scroll mode, madctl parameter mv shoul d be set to 0-this only affects the frame memory write. tfa[8:0]+vsa[8:0]+bfa[8:0] must equal to 320 or abnoemal display will be observed. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes t op - le f t (0,0) top fixed area tfa [8:0] scroll fixed area v s f a [ 8 :0] first line read from b o tt o m f ixe d ar ea bfa [8:0] t op - le f t (0,0) bottom fixed area b f a [ 8 :0] s c r ol l fi xe d ar ea vsfa [8:0] top fixed area t f a [ 8 :0] first line read from frame memory
ST7787 ver. 1.7 2008.04.18 145 default default value status tfa8 tfa[7:0] vfa8 vfa[7:0] bfa8 bfa[7:0] power on sequence 0h 00h 1h 40h 0h 00h s/w reset 0h 00h 1h 40h 0h 00h h/w reset 0h 00h 1h 40h 0h 00h flow chart note: the frame memory window size must be defined correctly otherwise undesirable image will be displayed. 1. to enter vertical scroll mode legend normal mo de scrlar (33h) 1 st & 2 nd parameter: tfa[8:0] 3 rd & 4 th parameter vsa[8:0] 5 th & 6 th parameter bfa[8:0] c o m m a nd parameter display action mode sequential transfer c a set ( 2ah) 1 s t & 2 n d parameter xs[7:0] 3 rd & 4 th parameter xe[7:0] re d e f i n e s th e fram e memory window that the scroll data will be define only required for non-rolling scrolling raset (2 1 st & 2 nd parameter ys[7:0] 3 rd & 4 th parameter ye[7:0] madctl (36h) parameter: m y , mx , m v ,m l , rgb r a m rw (2c h) scr ol l i mage d a ta vscs a d ( 3 7 h) 1 s t & 2 n d parameter ss a[7:0]1 scro l l mo de opt i o n al C it may be necessary to redefine the frame memory write direction.
ST7787 ver. 1.7 2008.04.18 146 note: scroll mode can be exit by both the normal di splay mode on (13h) and partial mode on (12h) commands. 2 . co n tin u ous scr o ll normal mode caset (2ah) 1 st &2 nd parameter xs[7:0] 3 rd & 4 th parameter xe[7:0] raset (2bh) l ege n d command parameter display action mode sequential transfer 1 s t & 2 n d parameter ys[7:0] 3 rd & 4 th parameter ye[7:0] r am rw (2c h) only require d for non-rollin g scrolling scro l l i mage da ta vscs a d (37 h) 1 s t & 2 nd parameter ssa[7:0]1 3. t o e x it ve rtical s c r o ll mo de scro l l m ode disoff (28h) noron ( 1 3 h ) / p t lon (12 h) opt i o n - to prevent tearing effect image display s c r ol l m o d e o ff r am rw (2c h) image data d1[17:0],d2[17:0] dn[17:0] d i son (29 h)
ST7787 ver. 1.7 2008.04.18 147 10.1.26 teoff (34h): tearing effect line off 34h teoff (tearing effect line off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teoff 0 1 - 0 0 1 1 0 1 0 0 (34h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to turn off (active low) the tearing effect output signal from the te signal lin e. restriction -this command has no effect when tearing effect out put is already off. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence off s/w reset off h/w reset off flow chart l ege n d t e lin e o u tp u t on c o mm an d par a m e t er te d is pl a y ac t i on t e l i n e o u t pu t of f m o sequential transfer
ST7787 ver. 1.7 2008.04.18 148 10.1.27 teon (35h): tearing effect line on 35h teon (tearing effect line on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teon 0 1 - 0 0 1 1 0 1 0 1 (35h) 1st parameter 1 1 - 0 0 0 0 0 0 0 telom note: - dont care, can be set to vddi or dgnd le vel description -this command is used to turn on the tearing effect output signal from the te signal line. -this output is not affected by changing madctl bit ml. -the tearing effect line on has one parameter, whic h describes the mode of the tearing effect output line. (-=dont care). when telom(m)=0: when telom m=1: note: during sleep in mode with tearing effect line on, tearing effect output pin will be active low. restriction -this command has no effect when tearing effect outp ut is already off. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tearing effect off & telom=0 s/w reset tearing effect off & telom=0 h/w reset tearing effect off & telom=0 flow chart ve rtical ti m e s c a l e t vd l t v dh the tearing effect output line consists of v - blanking information only . the tearing effect output line consists of both v - blanking and h - blinking information. ve rtical time scale t vd l t v dh t e l i n e o u tp u t of f teon (35h) 1 st parameter: (m) l e ge nd command parameter display action m od e t e lin e o u tp u t on sequential
ST7787 ver. 1.7 2008.04.18 149 10.1.28 madctl (36h): memory data access control 36h madctl (memory data access control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) madctl 0 1 - 0 0 1 1 0 1 1 0 (36h) 1st parameter 1 1 - my mx mv ml rgb mh 0 0 note: - dont care, can be set to vddi or dgnd le vel description -this command defines read/ write scanning directio n of frame memory. -this command makes no change on the other driver s tatus. -bit assignment bit name description my row address order mx column address order mv row/column exchange these 3bits controls mcu to memory write/read direction. (see section 9.12) ml vertical refresh order lcd vertical refresh direction control 0 = lcd vertical refresh top to bottom 1 = lcd vertical refresh bottom to top rgb rgb-bgr order color selector switch control 0 = r g b color filter panel, 1 = b g r color filter panel mh horizontal refresh order lcd horizontal refresh direction control 0 = lcd horizontal refresh left to right 1 = lcd horizontal refresh right to left sen t 3 r d sent 2nd sent first me m o r y d i s pl ay se n t la s t sen t la s t m l: v ert i cal refres h or d er memory display sent first sent 2nd se n t 3rd t op - le f t (0,0) m l = 0 t op - le f t (0,0) m l = 1 rgb: rgb - bgr order r g b s ig1 rgb = 0 driver ic r g b s ig2 r g b s ig 240 r g b si g 1 rg b = 1 driver ic r g b sig 2 r g b sig 240 s ig1 r g b r g s ig2 r g b r g b lcd p an el s ig 2 40 r g b r g b si g 1 b g r si g 2 b g r b g r l cd pa n el sig 240 b g r b g r r g b r g b r g b r g b r g b r g b b g r b g r b g r b g r b g r b g r r g b r g b r g b r g b r g b r g b
ST7787 ver. 1.7 2008.04.18 150 description restriction d1 and d0 of the 1 st parameter are set to 00 internally. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence my=0,mx=0,mv=0,ml=0,rgb=0, mh=0 s/w reset no change h/w reset my=0,mx=0,mv=0,ml=0,rgb=0, mh=0 flow chart l e ge nd command parameter display action m od e sequential t op - le f t (0,0) m h: h o r i z o nt a l refres h order top-left (0,0) me m o r y me m o r y ml = 0 m l = 1 t op - le f t (0,0) d i s p l ay t op - le f t (0,0) d i s p l ay sent first sent 2nd sent 3rd sent last sent last sent 3rd sent 2nd sent first madctl (36 h ) 1 st parameter: my, mx, ml, rgb, mh
ST7787 ver. 1.7 2008.04.18 151 10.1.29 vscsad (37h): vertical scroll start address of ram 37h vscsad (vertical scroll start address of ram) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vscsad 0 1 - 0 0 1 1 0 1 1 1 (37h) 1 st parameter 1 1 - - - - - - - - ssa8 2 nd parameter 1 1 - ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 note: - dont care, can be set to vddi or dgnd le vel description -this command is used together with vertical s crolling definition (33h). these two commands descr ibe the scrolling area and the scrolling mode. - the vertical scrolling start address command has on e parameter which describes which line in the frame memory will be written as the first line after the last line of the top fixed area on the display as i llustrated below: -this command start the scrolling. -exit from v-scrolling mode by commands partial mod e on (12h) or normal mode on (13h). when madctl ml= 0 example: when top fixed area=bottom fixed area=00, vertical scrolling area=320 and vertical scrolling pointer ssa= 3. when madctl ml = 1 example: when top fixed area= bottom fixed area=00, vertical scrolling area=320 and ssa= 3 note: -when new pointer position and picture data a re sent, the result on the display will happen at t he next panel scan to avoid tearing effect. -ssa refers to the frame memory scan address. restriction -since the value of the vertical scrolling start ad dress is absolute (with reference to the frame memory), it must not enter the fixed area (defined by vertical scrolling definition (33h)- otherwise undesirable image will be displayed on the panel. ssa[7:0] is based on 1-line unit. -ssa[7:0] = 0000h, 0001h, 0002h, 0003h, , 00a1h register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes t op - le f t (0,0) ssa[7:0] s c r ol l s t a rt a ddr e ss (e x a mp l e) scan address memory display 0 g1 1 g2 2 g3 3 g4 O | O | 318 g319 319 g320 t op - le f t (0,0) ssa[7:0] s c r ol l s t a rt a ddr e ss (e x am pl e) scan address memory display 319 g1 318 g2 O g3 O g4 3 | 2 | 1 g319 0 g320
ST7787 ver. 1.7 2008.04.18 152 default status default value power on sequence 0000h s/w reset 0000h h/w reset 0000h flow chart see vertical scrolling definition (33h) description.
ST7787 ver. 1.7 2008.04.18 153 10.1.30 idmoff (38h): idle mode off 38h idmoff (idle mode off) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmoff 0 1 - 0 0 1 1 1 0 0 0 (38h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to recover from idle mode on. -there will be no abnormal visible effect on the di splay mode change transition. -in the idle off mode, 1. lcd can display 4096, 65k or 262k colors. 2. normal frame frequency is applied. restriction -this command has no effect when module is already i n idle off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off flow chart l e ge nd i dl e mode on co mm a n d param e t er id m o f f (38 h) d is pl ay ac t i on id l e mode o ff m o de sequential tra n sfer
ST7787 ver. 1.7 2008.04.18 154 10.1.31 idmon (39h): idle mode on 39h idmon (idle mode on) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmoff 0 1 - 0 0 1 1 1 0 0 1 (39h) 1st parameter no parameter - note: - dont care, can be set to vddi or dgnd le vel description -this command is used to enter into idle mode on. -there will be no abnormal visible effect on the di splay mode change transition. -in the idle on mode, 1. color expression is reduced. the primary and the secondary colors using msb of each r,g and b in the frame memory, 8 color depth data is displayed. 2. 8-color mode frame frequency is applied. 3. exit from idmon by idle mode off (38h) command color r 5 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 b 4 b 3 b 4 b 1 b 0 black 0xxxxx 0xxxxx 0xxxxx blue 0xxxxx 0xxxxx 1xxxxx red 1xxxxx 0xxxxx 0xxxxx magenta 1xxxxx 0xxxxx 1xxxxx green 0xxxxx 1xxxxx 0xxxxx cyan 0xxxxx 1xxxxx 1xxxxx yellow 1xxxxx 1xxxxx 0xxxxx white 1xxxxx 1xxxxx 1xxxxx restriction this command has no effect when module is already in idle on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off t op - le f t (0, 0 ) (e x amp l e) me m o ry di s p lay
ST7787 ver. 1.7 2008.04.18 155 flow chart leg en d i d le mo d e on c o m m a nd p a rameter id m off (3 8h) d i s p lay a ct i on i d l e mo d e off m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 156 10.1.32 colmod (3ah): interface pixel format 3ah colmod (3ah): interface pixel format inst / para d/cx wrx rdx d17- 8 d7 d6 d5 d4 d3 d2 d1 d0 (code) colmod 0 1 - 0 0 1 1 1 0 1 0 (3ah) 1st parameter 1 1 - vipf3 vipf2 vipf1 vipf0 d3 ifpf2 ifpf1 ifpf0 note: - dont care, can be set to vddi or dgnd le vel description this command is used to define the format of rgb pic ture data, which is to be transferred via the mcu interface (ifpf) and rgb interface (vipf). the fo rmats are shown in the table: others are no define and invalid ifpf[2:0] mcu interface color format 011 3 12-bit/pixel 101 5 16-bit/pixel 110 6 18-bit/pixel others are no define and invalid vipf[3:0] rgb interface color format 0101 5 16-bit/pixel (1-time data transfer) 0110 6 18-bit/pixel (1-time data transfer) 1110 14 8-bit/pixel (3-times data transfer) note1: in 12-bit/pixel, 16-bit/pixel or 18-bit/pixe l mode, the lut is applied to transfer data into th e frame memory. note2: when rgb i/f the 12-bit/pixel dont care restriction there is no visible effect until the frame memory i s written to. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value ifpf[2:0] vipf[3:0] power on sequence 0110(18-bit/pixel) 0110(18-bit/pixel) s/w reset no change no change h/w reset 0110(18-bit/pixel) 0110(18-bit/pixel) flow chart 18 - bi t/p i x el m o de l ege n d c o m m a nd col m od (3 a h) 1 st parameter: p[2:0]=111 p a r a met er display action mo de 1 6 - bi t/p i x el m o de sequential transfer
ST7787 ver. 1.7 2008.04.18 157 10.1.33 otp-process (3fh): otp-process 3fh otp-process inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gmctrp1 0 - 1 - 0 0 1 1 1 1 1 1 (3fh) 1 st parameter 1 - 1 - 1 1 0 0 1 0 1 0 cah 2 rd parameter 1 - 1 - 0 0 0 0 0 0 ini 0 description -while extc is fixed to l. please set ini to 1 for enable otp rogramming -while extc is fixed to l please set ini to 0 for disable otp programing restriction -if this register not using the register need be re served. - after adjust the c5h command(vcomh voltage) and c6h com mand(vcomac voltage), vpp connect R 7.5v. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence not fixed s/w reset 00h h/w reset 00h flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: ------------------ otp - process ( fa h )
ST7787 ver. 1.7 2008.04.18 158 10.1.34 rdid1 (dah): read id1 value dah rdid1 (read id1 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid1 0 1 - 1 1 0 1 1 0 1 0 (dah) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 note: - dont care, can be set to vddi or dgnd le vel description -this read byte returns 8-bit lcd modules manufact urer id -the 1 st parameter is dummy data -the 2 nd parameter (id17 to id10): lcd modules manufacture r id. note: see command rddid (04h), 2 nd parameter. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence ff s/w reset ff h/w reset ff flow chart s e rial i/f m od e rdid1 (dah) send 2 nd parameter: i d 1[7:0] parti a l i/f mod e rdid1 (dah) du m my read host dr iver le g e n d command parameter display action send 2 nd parameter: id1[7:0] m od e sequential transfer
ST7787 ver. 1.7 2008.04.18 159 10.1.35 rdid2 (dbh): read id2 value dbh rdid2 (read id2 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid2 0 1 - 1 1 0 1 1 0 1 1 (dbh) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 note: - dont care, can be set to vddi or dgnd le vel description -this read byte returns 8-bit lcd module/driver ver sion id -the 1 st parameter is dummy data -the 2 nd parameter (id26 to id20): lcd module/driver version id -parameter range: id=80h to ffh note: see command rddid (04h), 3 rd parameter. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence ff s/w reset ff h/w reset ff flow chart s e ri a l i/f mo d e rdid2 (dbh) :send 2 nd parameter i d 2[ 7 :0] parti a l i/f mo d e rdid2 (dbh) du m m y r ead host dr iver l e ge nd command parameter display a ct ion send 2 nd paramete r: id2[7:0] m od e sequential transfer
ST7787 ver. 1.7 2008.04.18 160 10.1.36 rdid3 (dch): read id3 value dch rdid3 (read id2 value) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid3 0 1 - 1 1 0 1 1 1 0 0 (dch) 1 st parameter 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 note: - dont care, can be set to vddi or dgnd le vel description -this read byte returns 8-bit lcd module/driver id. -the 1 st parameter is dummy data -the 2 nd parameter (id37 to id30): lcd module/driver id. note: see command rddid (04h), 4 th parameter. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence ff s/w reset ff h/w reset ff flow chart seri a l i/f mo d e rdid3 (dch) send 2 nd parameter: id3[7:0] part rdid3 (dc h) d umm y r ead host dr i v er l ege n d command parameter display ac t i on s e nd 2 n d p a r a m e t e r: id3[7:0] m o d e sequential transfer
ST7787 ver. 1.7 2008.04.18 161 10.2.1 rgbctr (b0h): rgb signal control b0h rgbctr (rgb signal control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rgbctr 0 1 - 1 0 1 1 0 0 0 0 (b0h) 1 st parameter 1 1 - 0 0 0 icm dp ep hsp vsp note: - dont care description -set the operation status on the rgb interface. the setting becomes effective as soon as the command is received. -icm: gram write/read frequency and data input select on the rgb interface icm write/ read frequency and input data select write cycle read cycle data input 0 pclk pclk d[17:0] 1 scl internal oscillator sda symbol name clock polarity set for rgb interface dp pclk polarity set 1 = data fetched at the falling edge 0 = data fetched at the rising edge ep enable polarity set 1 = low enable for rgb interface 0 = high enable for rgb interface hsp hsync polarity set 1 = high level sync clock 0 = low level sync clock vsp vsync polarity set 1 = high level sync clock 0 = low level sync clock restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value icm dp/ep/hsp/vsp power on sequence s/w reset h/w reset flow chart ------------------ rgbc t r (b0 h ) 1 s t parameter: icm, dw, dp, e p , hs p , vsp le g e n d command parameter di s p lay action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 162 10.2.2 frmctr1 (b1h): frame rate control (in normal mode/ full colors) b1h frmctr1 (frame rate control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr1 0 1 - 1 0 1 1 0 0 0 1 (b1h) 1 st parameter 1 1 - --- rtna[6] rtna[5] rtna[4] rtna[3] rtna[2] rtna[1] rtna[0] - 2 nd parameter 1 1 - --- --- --- fpa[4] fpa[3] fpa[2] fpa[1] fpa[0] - 3th parameter - --- --- --- bpa[4] bpa[3] bpa[2] bpa[1] bpa[0] note: - dont care description -set the frame frequency of the full colors normal mode. -the frame frequency need to meet 60hz 5% in this mode. rtna[6:0] frame rate rtna[6:0] frame rate 0101000 40 90 1010100 84 43 0101001 41 88 1010101 85 43 0101010 42 86 1010110 86 42 0101011 43 84 1010111 87 42 0101100 44 82 1011000 88 41 0101101 45 80 1011001 89 41 0101110 46 78 1011010 90 40 0101111 47 77 1011011 91 40 0110000 48 75 1011100 92 40 0110001 49 74 1011101 93 39 0110010 50 72 1011110 94 39 0110011 51 71 1011111 95 38 0110100 52 70 1100000 96 38 0110101 53 68 1100001 97 37 0110110 54 67 1100010 98 37 0110111 55 66 1100011 99 37 0111000 56 65 1100100 100 36 0111001 57 63 1100101 101 36 0111010 58 62 1100110 102 36 0111011 59 61 1100111 103 35 0111100 60 60 1101000 104 35 0111101 61 59 1101001 105 35 0111110 62 59 1101010 106 34 0111111 63 57 1101011 107 34 1000000 64 57 1101100 108 34 1000001 65 56 1101101 109 33 1000010 66 55 1101110 110 33 1000011 67 54 1101111 111 33 1000100 68 53 1110000 112 32 1000101 69 53 1110001 113 32 1000110 70 52 1110010 114 32 1000111 71 51 1110011 115 32 1001000 72 51 1110100 116 31 1001001 73 50 1110101 117 31 1001010 74 49 1110110 118 31 1001011 75 48 1110111 119 31 1001100 76 48 1111000 120 30 1001101 77 47 1111001 121 30 1001110 78 47 1111010 122 30 1001111 79 46 1111011 123 30 1010000 80 45 1111100 124 29 1010001 81 45 1111101 125 29 1010010 82 44 1111110 126 29 1010011 83 44 1111111 127 29 note: osc output fre. is 1.2mhz, fpa=02h and bpa=0 2h
ST7787 ver. 1.7 2008.04.18 163 fpa[4:0] timing bpa[4:0] timing 00000 0 0 line 00000 0 0 line 00001 1 1 line 00001 1 1 line 00010 2 2 lines 00010 2 2 lines 00011 3 3 lines 00011 3 3 lines 00100 4 4 lines 00100 4 4 lines 00101 5 5 lines 00101 5 5 lines 00110 6 6 lines 00110 6 6 lines 00111 7 7 lines 00111 7 7 lines 01000 8 8 lines 01000 8 8 lines 01001 9 9 lines 01001 9 9 lines 01010 10 10 lines 01010 10 10 lines 01011 11 11 lines 01011 11 11 lines 01100 12 12 lines 01100 12 12 lines 01101 13 13 lines 01101 13 13 lines 01110 14 14 lines 01110 14 14 lines 01111 15 15 lines 01111 15 15 lines 10000 16 16 lines 10000 16 16 lines 10001 17 17 lines 10001 17 17 lines 10010 18 18 lines 10010 18 18 lines 10011 19 19 lines 10011 19 19 lines 10100 20 20 lines 10100 20 20 lines 10101 21 21 lines 10101 21 21 lines 10110 22 22 lines 10110 22 22 lines 10111 23 23 lines 10111 23 23 lines 11000 24 24 lines 11000 24 24 lines 11001 25 25 lines 11001 25 25 lines 11010 26 26 lines 11010 26 26 lines 11011 27 27 lines 11011 27 27 lines 11100 28 28 lines 11100 28 28 lines 11101 29 29 lines 11101 29 29 lines 11110 30 30 lines 11110 30 30 lines 11111 31 31 lines 11111 31 31 lines restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status rtna fpa bpa power on sequence 36h 02h 02h s/w reset 36h 02h 02h h/w reset 36h 02h 02h
ST7787 ver. 1.7 2008.04.18 164 flow chart ------------- f r m c t r1 (b1 h) 1 st parameter: 2 nd parameter: 3 rd parameter:: le g e n d command parameter di s p lay action m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 165 10.2.3 frmctr2 (b2h): frame rate control (in idle m ode/ 8-colors) b2h frmctr2 (frame rate control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr2 0 1 - 1 0 1 1 0 0 1 0 (b2h) 1 st parameter 1 1 - --- rtnb[6] rtnb[5] rtnb[4] rtnb[3] rtnb[2] rtnb[1] rtnb[0] - 2 nd parameter 1 1 - --- --- --- fpb[4] fpb[3] fpb[2] fpb[1] fpb[0] - 3th parameter 1 1 - --- --- --- bpb[4] bpb[3] bpb[2] bpb[1] bpb[0] note: - dont care description -set the frame frequency of the idle mode. -the frame frequency need to meet 60hz 5% in this mode. rtnb[6:0] frame rate rtnb[6:0] frame rate 0101000 40 87 1010100 84 42 0101001 41 85 1010101 85 41 0101010 42 83 1010110 86 41 0101011 43 81 1010111 87 40 0101100 44 79 1011000 88 40 0101101 45 78 1011001 89 40 0101110 46 76 1011010 90 39 0101111 47 74 1011011 91 39 0110000 48 73 1011100 92 38 0110001 49 71 1011101 93 38 0110010 50 70 1011110 94 37 0110011 51 69 1011111 95 37 0110100 52 67 1100000 96 37 0110101 53 66 1100001 97 36 0110110 54 65 1100010 98 36 0110111 55 64 1100011 99 36 0111000 56 63 1100100 100 35 0111001 57 62 1100101 101 35 0111010 58 60 1100110 102 35 0111011 59 59 1100111 103 34 0111100 60 58 1101000 104 34 0111101 61 58 1101001 105 34 0111110 62 57 1101010 106 33 0111111 63 56 1101011 107 33 1000000 64 55 1101100 108 33 1000001 65 54 1101101 109 32 1000010 66 53 1101110 110 32 1000011 67 52 1101111 111 32 1000100 68 52 1110000 112 31 1000101 69 51 1110001 113 31 1000110 70 50 1110010 114 31 1000111 71 50 1110011 115 31 1001000 72 49 1110100 116 30 1001001 73 48 1110101 117 30 1001010 74 47 1110110 118 30 1001011 75 47 1110111 119 30 1001100 76 46 1111000 120 29 1001101 77 46 1111001 121 29 1001110 78 45 1111010 122 29 1001111 79 44 1111011 123 29 1010000 80 44 1111100 124 28 1010001 81 43 1111101 125 28 1010010 82 43 1111110 126 28 1010011 83 42 1111111 127 28 note: osc output fre. is 1.2mhz, fpa=02h and bpa=02 h
ST7787 ver. 1.7 2008.04.18 166 fpb[4:0] timing bpb[4:0] timing 00000 0 0 line 00000 0 0 line 00001 1 1 line 00001 1 1 line 00010 2 2 lines 00010 2 2 lines 00011 3 3 lines 00011 3 3 lines 00100 4 4 lines 00100 4 4 lines 00101 5 5 lines 00101 5 5 lines 00110 6 6 lines 00110 6 6 lines 00111 7 7 lines 00111 7 7 lines 01000 8 8 lines 01000 8 8 lines 01001 9 9 lines 01001 9 9 lines 01010 10 10 lines 01010 10 10 lines 01011 11 11 lines 01011 11 11 lines 01100 12 12 lines 01100 12 12 lines 01101 13 13 lines 01101 13 13 lines 01110 14 14 lines 01110 14 14 lines 01111 15 15 lines 01111 15 15 lines 10000 16 16 lines 10000 16 16 lines 10001 17 17 lines 10001 17 17 lines 10010 18 18 lines 10010 18 18 lines 10011 19 19 lines 10011 19 19 lines 10100 20 20 lines 10100 20 20 lines 10101 21 21 lines 10101 21 21 lines 10110 22 22 lines 10110 22 22 lines 10111 23 23 lines 10111 23 23 lines 11000 24 24 lines 11000 24 24 lines 11001 25 25 lines 11001 25 25 lines 11010 26 26 lines 11010 26 26 lines 11011 27 27 lines 11011 27 27 lines 11100 28 28 lines 11100 28 28 lines 11101 29 29 lines 11101 29 29 lines 11110 30 30 lines 11110 30 30 lines 11111 31 31 lines 11111 31 31 lines restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status rtnb fpb bpb power on sequence 38h 02h 02h s/w reset 38h 02h 02h h/w reset 38h 02h 02h
ST7787 ver. 1.7 2008.04.18 167 flow chart ------------- f r m c t r1 (b 2 h) 1 st parameter: 2 nd parameter: 3 rd parameter le g e n d command parameter di s p lay action m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 168 10.2.3 frmctr3 (b3h): frame rate control (in partia l mode/ full colors) b3h frmctr3 (frame rate control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) frmctr3 0 1 - 1 0 1 1 0 0 1 1 (b3h) 1 st parameter 1 1 - - rtnc[6] rtnc[5] rtnc[4] rtnc[3] rtnc[2] rtnc[1] rtnc[0] - 2 nd parameter 1 1 - - - - fpc[4] fpc[3] fpc[2] fpc[1] fpc[0] 3 rd arameter 1 1 - - - - bpc[4] bpc[3] bpc[2] bpc[1] bpc[0] 4 th parameter 1 1 --- rtnd[6] rtnd[5] rtnd[4] rtnd[3] rtnd[2] rtnd[1] rtnd[0] 5 th parameter 1 1 - - - - fpd[4] fpd[3] fpd[2] fpd[1] fpd[0] 6 th parameter 1 1 - - - - bpd[4] bpd[3] bpd[2] bpd[1] bpd[0] - note: - dont care description -set the frame frequency of the partial mode/ full colors. -when the display is frame inversion the frame freq uency need to meet 65hz 5% in this mode. -when the display is line inversion the frame frequ ency need to meet 70hz 5% in this mode. rtnc[6:0] frame rate rtnc[6:0] frame rate 0101000 40 87 1010100 84 42 0101001 41 85 1010101 85 41 0101010 42 83 1010110 86 41 0101011 43 81 1010111 87 40 0101100 44 79 1011000 88 40 0101101 45 77 1011001 89 39 0101110 46 76 1011010 90 39 0101111 47 74 1011011 91 39 0110000 48 73 1011100 92 38 0110001 49 71 1011101 93 38 0110010 50 70 1011110 94 37 0110011 51 68 1011111 95 37 0110100 52 67 1100000 96 36 0110101 53 66 1100001 97 36 0110110 54 65 1100010 98 36 0110111 55 63 1100011 99 35 0111000 56 62 1100100 100 35 0111001 57 61 1100101 101 35 0111010 58 60 1100110 102 34 0111011 59 59 1100111 103 34 0111100 60 58 1101000 104 34 0111101 61 57 1101001 105 33 0111110 62 56 1101010 106 33 0111111 63 55 1101011 107 33 1000000 64 54 1101100 108 32 1000001 65 54 1101101 109 32 1000010 66 53 1101110 110 32 1000011 67 52 1101111 111 32 1000100 68 51 1110000 112 31 1000101 69 51 1110001 113 31 1000110 70 50 1110010 114 31 1000111 71 49 1110011 115 30 1001000 72 49 1110100 116 30 1001001 73 48 1110101 117 30 1001010 74 47 1110110 118 30 1001011 75 47 1110111 119 29 1001100 76 46 1111000 120 29 1001101 77 45 1111001 121 29 1001110 78 45 1111010 122 29 1001111 79 44 1111011 123 28 1010000 80 44 1111100 124 28 1010001 81 43 1111101 125 28 1010010 82 43 1111110 126 28 1010011 83 42 1111111 127 28
ST7787 ver. 1.7 2008.04.18 169 note: osc output fre. is 1.2mhz, fpa=02h and bpa=02 h rtnd[6:0] frame rate rtnd[6:0] frame rate 0101000 40 867 1010100 84 42 0101001 41 85 1010101 85 41 0101010 42 83 1010110 86 41 0101011 43 81 1010111 87 40 0101100 44 79 1011000 88 40 0101101 45 77 1011001 89 39 0101110 46 75 1011010 90 39 0101111 47 74 1011011 91 38 0110000 48 72 1011100 92 38 0110001 49 71 1011101 93 38 0110010 50 69 1011110 94 37 0110011 51 68 1011111 95 37 0110100 52 67 1100000 96 36 0110101 53 66 1100001 97 36 0110110 54 64 1100010 98 36 0110111 55 63 1100011 99 35 0111000 56 62 1100100 100 35 0111001 57 61 1100101 101 35 0111010 58 60 1100110 102 34 0111011 59 59 1100111 103 34 0111100 60 58 1101000 104 34 0111101 61 57 1101001 105 33 0111110 62 56 1101010 106 33 0111111 63 55 1101011 107 33 1000000 64 55 1101100 108 32 1000001 65 54 1101101 109 32 1000010 66 53 1101110 110 32 1000011 67 52 1101111 111 32 1000100 68 51 1110000 112 31 1000101 69 51 1110001 113 31 1000110 70 50 1110010 114 31 1000111 71 49 1110011 115 30 1001000 72 49 1110100 116 30 1001001 73 48 1110101 117 30 1001010 74 47 1110110 118 30 1001011 75 47 1110111 119 29 1001100 76 46 1111000 120 29 1001101 77 45 1111001 121 29 1001110 78 45 1111010 122 29 1001111 79 44 1111011 123 28 1010000 80 44 1111100 124 28 1010001 81 43 1111101 125 28 1010010 82 43 1111110 126 28 1010011 83 42 1111111 127 28 note: osc output fre. is 1.2mhz, fpa=02h and bpa=02 h restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes
ST7787 ver. 1.7 2008.04.18 170 default default value status rtnc fpc bpc rtnd fpd bpd power on sequence 36h 02h 02h 38h 02h 02h s/w reset 36h 02h 02h 38h 02h 02h h/w reset 36h 02h 02h 38h 02h 02h flow chart ------------- f r m c t r1 (b 3 h) 1 st parameter: 2 nd parameter: 3 rd parameter: . . 6 th parameter: le g e n d command paramete r di s p lay action m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 171 10.2.5 invctr (b4h): display inversion control b4h invctr (display inversion control) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invctr 0 1 - 1 0 1 1 0 1 0 0 (b4h) 1 st parameter 1 1 - 0 0 0 0 0 nla nlb nlc 02h note: - dont care description -display inversion mode control -nla: inversion setting in full colors normal mode ( normal mode on) nla inversion setting in full colors normal mode 0 line inversion 1 frame inversion -nlb: inversion setting in idle mode (idle mode on) nlb inversion setting in idle mode 0 line inversion 1 frame inversion -nlc: inversion setting in full colors partial mode ( partial mode on / idle mode off) nlc inversion setting in full colors partial mode 0 line inversion 1 frame inversion restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value nla nlb nlc b4h power on sequence 0d 1d 0d 02h s/w reset 0d 1d 0d 02h h/w reset 0d 1d 0d 02h flow chart ------------- invctr (b4h) ] 1 st parameter: nla, nlb, nlc le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 172 10.2.6 rgbbpctr (b5h): rgb interface blanking porch setting b5h rgbpset (rgb interface blanking porch setting) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rgbbpctr 0 1 - 1 0 1 1 0 1 0 1 (b5h) 1 st parameter 1 1 - --- --- --- --- vfp[3] vfp[2] vfp[1] vfp[0] - 2 nd parameter 1 1 - --- --- --- --- vbp[3] vbp[2] vbp[1] vbp[0] - 3 rd parameter 1 1 --- --- --- --- hfp[3] hfp[2] hfp[1] hfp[0] 4 th parameter 1 1 --- --- --- --- hbp[3] hbp[2] hbp[1] hbp[0] note: - dont care description -set the blanking porch in the rgb interface -the detail settings are designed by driver maker. restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status vfp[3:0] vbp[3:0] hfp[3:0] hbp[3:0] power on sequence 00h 02h 09h 09h s/w reset 00h 02h 09h 09h h/w reset 00h 02h 09h 09h flow chart ------------- rgbbpctr1 (b5h) 1 st parameter: 2 nd parameter: 3 rd parameter: 4 th parameter: le g e n d command parameter di s p lay action m ode sequential transfer
ST7787 ver. 1.7 2008.04.18 173 10.2.7 disset5 (b6h): display function set 5 b6h disset (display function set 5) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) disset5 0 1 - 1 0 1 1 0 1 1 0 (b6h) 1 st parameterr 1 1 - --- --- no1 no0 std1 std0 eq1 eq0 02h 2 nd paramete 1 1 - --- --- --- --- ptg1 ptg0 pt1 pt0 02h note: - dont care description -1 st parameter: set output waveform relation. -no[1:0]: set the amount of non-overlap of the gate output no[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 2 clock cycle 8 clock cycle 01 1 4 clock cycle 16 clock cycle 10 2 8 clock cycle 32 clock cycle 11 3 10 clock cycle 40 clock cycle -sdt[1:0]: set delay amount from gate signal falling edge of the source output. sdt[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 1 clock cycle 4 clock cycle 01 1 2 clock cycle 8 clock cycle 10 2 3 clock cycle 12 clock cycle 11 3 4 clock cycle 16 clock cycle -eq[1:0]: set the equalizing period -2 nd parameter: set the output waveform in non-display ar ea. -ptg[1:0]: determine gate output in a non-display ar ea in the partial mode -pt[1:0]: determine source /vcom output in a non-disp lay area in the partial mode eq[1:0] amount of non-overlap of the gate output refer the internal oscillator refer the pclk 00 0 0 clock cycle 0 clock cycle 01 1 4 clock cycle 16 clock cycle 10 2 6 clock cycle 24 clock cycle 11 3 8 clock cycle 32 clock cycle ptg[1:0] gate output in a non-display area 00 0 normal scan 01 1 fix on vgl 10 2 fix on vgl 11 3 fix on vgl source output on non-display area vcom output on non-display area pt[1:0] positive negative positive negative 00 0 v63 v0 vcoml vcomh 01 1 v0 v63 vcoml vcomh 10 2 agnd agnd agnd agnd 11 3 hi-z hi-z agnd agnd restriction -if this register not using the register need be re served. gn gate non-overlap period gn+1 s n vcom delay ti m e f or source output eq per i od
ST7787 ver. 1.7 2008.04.18 174 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value no[1:0] std[1:0] eq[1:0] ptg[1:0] pt[1:0] power on sequence 00 00 10 00 10 s/w reset 00 00 10 00 10 h/w reset 00 00 10 00 10 flow chart le g e n d command parameter display action mode sequential transfer :1 s t parameter no[1:0], std[1:0], eq[1:0] 2 nd parameter: p t g[ 1 :0], p t [1:0] ----- ------------- disse t 5 (b6 h )
ST7787 ver. 1.7 2008.04.18 175 10.2.8 vsyncout (bch): bch vsyncout inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vsyncout 0 1 - 1 0 1 1 1 1 0 0 (bch) 1 st parameter no parameter note: - dont care description this command comes off external vsync a display synch ronous. operation shifts to an internal synchronous mode by the vsyncout command while external vsync is synchronizing. vsyncout command is recognized fram e synchronously. the shift operation becomes the same for the vsyncout command issued with in the range of the inside of the figure. restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence off s/w reset off h/w reset off flow chart le g e n d command parameter display action mode sequential transfer e x xternal vsync enable vsyncout(bch) e x ternal vsync disable
ST7787 ver. 1.7 2008.04.18 176 10.2.9 vsyncin (bdh): bdh vsyncin inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vsyncout 0 1 - 1 0 1 1 1 1 0 1 (bdh) 1 st parameter no parameter note: - dont care description -the frame to which the command is input finishes se nding data by an internal vertical synchronizing signal. afterward, an external vertical synchronizin g signal is waiting for at the rest period. the operation after that becomes external synchronous. operation enters the rest period when the transmission of data ends for one frame while the ex ternal is synchronizing. wait: synchronous waiting period. operation is external vsync perceives l level of th e vsync signal and internal operate and after synchronization t, scans the display for one frame. external vsync signal through te pin. operation enters the synchronous waiting period agai n when the display sacanning ends. restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence off s/w reset off h/w reset off flow chart le g e n d command parameter display action m ode sequential transfer e x xternal vsync disable vsyncout(bdh) e x ternal vsync enable
ST7787 ver. 1.7 2008.04.18 177 10.2.10 pwctr1 (c0h): power control 1 c0h pwctr1 (power control 1) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr1 0 1 - 1 1 0 0 0 0 0 0 (c0h) 1 st parameter 1 1 - 0 0 0 vrh4 vrh3 vrh2 vrh1 vrh0 note: - dont care description -set the gvdd and voltage vrh[4:0] gvdd 00000 0 5.00 00001 1 4.75 00010 2 4.70 00011 3 4.65 00100 4 4.60 00101 5 4.55 00110 6 4.50 00111 7 4.45 01000 8 4.40 01001 9 4.35 01010 10 4.30 01011 11 4.25 01100 12 4.20 01101 13 4.15 01110 14 4.10 01111 15 4.05 10000 16 4.00 10001 17 3.95 10010 18 3.90 10011 19 3.85 10100 20 3.80 10101 21 3.75 10110 22 3.70 10111 23 3.65 11000 24 3.60 11001 25 3.55 11010 26 3.50 11011 27 3.45 11100 28 3.40 11101 29 3.35 11110 30 3.25 11111 31 3.00 restriction -if this register not using the register need be re served. -the deviation value of gvdd between with measurement and specification: max <=50mv -the deviation value of vci1 between with measurement and specification: max <= 1% register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value lcm1, lcm0 = 01 tr lc type vrh[4:0] power on sequence 10000 s/w reset 10000 h/w reset 10000
ST7787 ver. 1.7 2008.04.18 178 flow chart le g e n d command parameter display action mode sequential transfer :1 s t parameter vrh[4:0] ------------------ pectr1 ( c0 h )
ST7787 ver. 1.7 2008.04.18 179 10.2.11 pwctr2 (c1h): power control 2 c1h pwctr2 (power control 2) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr2 0 1 - 1 1 0 0 0 0 0 1 (c1h) 1 st parameter 1 1 - vgh3 vgh2 vgh1 vgh0 vgl3 vgl2 vgl1 vgl0 2 nd parameter 1 1 - -- -- -- -- -- got2 got1 got0 note: - dont care description -set the avdd, vcl, vgh and vgl supply power level vgh[2:0]/vgl[2:0] vgh vgl 0000 0 x -5.0 0001 1 x -5.5 0010 2 x -6.0 0011 3 x -6.5 0100 4 x -7.0 0101 5 12 -9.0 0110 6 12.5 -9.5 0111 7 13.0 -10.0 1000 8 13.5 -10.5 1001 9 14.0 -11.0 1010 10 14.5 -11.5 1011 11 15.0 -12.0 1100 12 15.5 -12.5 1101 13 16.0 -13.0 1110 14 16.5 -13.5 1111 15 x -14.0 unit(v) - got [2:0]: define vgh2 level period. got[2:0] uc mode osc clk rgb pixel clk 000 0 0 001 4 16 010 6 24 011 9 36 100 11 44 101 14 56 110 16 64 111 19 76 note: when vci1=2.5v, vdd=2.5v,set-up cycle 1 effectiv e=95%, set-up cycle 2 effective=98%, restriction -if this register not using the register need be re served. -the deviation value of vgh/ vgl between with measu rement and specification: max: vgh-vgl<=1v -vgh-vgl <= 32v
ST7787 ver. 1.7 2008.04.18 180 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value got[2:0] vgh[3:0] vgl[3:0] power on sequence 00h c0h 80h s/w reset 00h c0h 80h h/w reset 00h c0h 80h flow chart le g e n d command parameter display action mode sequential transfer :1 s t parameter .2 nd parameter ------------------ pwctr2 ( c1 h )
ST7787 ver. 1.7 2008.04.18 181 10.2.12 pwctr3 (c2h): power control 3 (in normal mo de/ full colors) c2h pwctr3 (power control 3) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr3 0 1 - 1 1 0 0 0 0 1 0 (c2h) 1 st parameter 1 1 - 0 0 0 0 0 apa2 apa1 apa0 2 nd parameter 1 1 - step1a _sel3 step1a _sel2 step1a _sel1 step1a _sel0 0 step2a _sel2 step2a _sel1 step2a _sel0 3 rd parameter 1 1 - 1 ldo5 _sel2 ldo5 _sel1 ldo5 _sel0 --- step4a _sel2 step4a _sel1 step4a _sel0 4 th parameter 1 1 - - step1ap _sel2 step1ap _sel1 step1ap _sel0 --- step2pa _sel2 step2pa _sel1 step2pa _sel0 5 th parameter 1 1 - - - - - step4pa _sel2 step4pa _sel1 step4pa _sel0 note: - dont care description -set the amount of current in operational amplifier in normal mode/full colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apa[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved -set the booster circuit step-up cycle in normal mod e/ full colors. step1a_sel[3:0] step-up cycle in booster circuit 1 0000 0 osc/2048 0001 1 osc/1024 0010 2 osc/512 0011 3 osc/128 0100 4 osc/64 0101 5 osc/16 0110 6 osc/8 0111 7 osc/4 1000 8 osc/2048 1001 9 osc/1024 1010 10 osc/512 1011 11 osc/128 1100 12 osc/64 1101 13 osc/16 1110 14 osc/8 1111 15 osc/4 unit:khz note:while step1a_sel3 setting to 0, the charge p ump circuit is selected to single mode. on the co ntray to dual mode. step2a_sel[2:0] step-up cycle in booster circuit 2 step4a_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/2048 000 0 osc/2048 001 1 osc/1024 001 1 osc/1024 010 2 osc/512 010 2 osc/512 011 3 osc/128 011 3 osc/128 100 4 osc/64 100 4 osc/64 101 5 osc/16 101 5 osc/16 110 6 osc/8 110 6 osc/8 111 7 osc/4 111 7 osc/4 unit:khz ldo5 [2:0] c1s(v) 000 0 4.5 001 1 4.6 010 2 4.7 011 3 4.8 100 4 4.9 101 5 5.0 110 6 5.1 111 7 x unit(v)
ST7787 ver. 1.7 2008.04.18 182 1. set the booster circuit step-up cycle during porch area in normal mode/ full colors. step1pa_sel[2:0] step-up cycle in booster circuit 1 step2pa_sel[2:0] step-up cycle in booster circuit 2 000 0 osc/2048 000 0 osc/2048 001 1 osc/1024 001 1 osc/1024 010 2 osc/512 010 2 osc/512 011 3 osc/128 011 3 osc/128 100 4 osc/64 100 4 osc/64 101 5 osc/16 101 5 osc/16 110 6 osc/8 110 6 osc/8 111 7 osc/4 111 7 osc/4 unit:khz step4pa_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/2048 001 1 osc/1024 010 2 osc/512 011 3 osc/128 100 4 osc/64 101 5 osc/16 110 6 osc/8 111 7 osc/4 unit:khz note: bclk is clock frequency for booster circuit restriction -if some parameter of the register not use the regi ster need to be reserved. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value apa[2:0] step1a _sel[3:0] step2a _sel[2:0] ste4a _sel[2:0] ldo5 _sel[2:0] step1pa _sel[3:0] step2pa _sel[2:0] ste4pa _sel[2:0] power on sequence 01h 0bh 03h 03h 00h 00h 00h 00h s/w reset 01h 0bh 03h 03h 00h 00h 00h 00h h/w reset 01h 0bh 03h 03h 00h 00h 00h 00h flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: apa[2:0] 2 nd parameter: step1a[3:0] & step2a[2:0] 3 rd parameter ldo5[2:0] &step2a[2:0] 4 th parameter step1pa[2:0] & step2pa[2:0] 5 th parameter step4pa[2:0] ------------------ pwctr3 (c2h)
ST7787 ver. 1.7 2008.04.18 183 10.2.13 pwctr4 (c3h): power control 4 (in idle mode / 8-colors) c3h pwctr4 (power control 4) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr4 0 1 - 1 1 0 0 0 0 1 1 (c3h) 1 st parameter 1 1 - 0 0 0 0 0 apb2 apb1 apb0 2 nd parameter 1 1 - step1b _sel3 step1b _sel2 step1b _sel1 step1b _sel0 0 step2b _sel2 step2b _sel1 step2b _sel0 3 rd parameter 1 1 step4b _sel2 step4b _sel1 step4b _sel0 4 th parameter 1 1 step1pb _sel2 step1pb _sel1 step1pb _sel0 step2pb _sel2 step2pb _sel1 step2pb _sel0 5 th parameter 1 1 step4pb _sel2 step4pb _sel1 step4pb _sel0 note: - dont care description -set the amount of current in operational amplifier in idle mode/8 colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apb[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved -set the booster circuit step-up cycle in idle mode /8 colors. step1b_sel[3:0] step-up cycle in booster circuit 1 0000 0 osc/2048 0001 1 osc/1024 0010 2 osc/512 0011 3 osc/128 0100 4 osc/64 0101 5 osc/16 0110 6 osc/8 0111 7 osc/4 1000 8 osc/2048 1001 9 osc/1024 1010 10 osc/512 1011 11 osc/128 1100 12 osc/64 1101 13 osc/16 1110 14 osc/8 1111 15 osc/4 unit:khz note:while step1b_sel3 setting to 0, the charge p ump circuit is selected to single mode. on the co ntray to dual mode. step2b_sel[2:0] step-up cycle in booster circuit 2 step4b_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/1024 000 0 osc/2048 001 1 osc/2048 001 1 osc/1024 010 2 osc/1024 010 2 osc/512 011 3 osc/512 011 3 osc/128 100 4 osc/128 100 4 osc/64 101 5 osc/64 101 5 osc/16 110 6 osc/16 110 6 osc/8 111 7 osc/8 111 7 osc/4
ST7787 ver. 1.7 2008.04.18 184 1. set the booster circuit step-up cycle during porch area in idle mode. step1pb_sel[2:0] step-up cycle in booster circuit 1 step2pb_sel[2:0] step-up cycle in booster circuit 2 000 0 osc/2048 000 0 osc/2048 001 1 osc/1024 001 1 osc/1024 010 2 osc/512 010 2 osc/512 011 3 osc/128 011 3 osc/128 100 4 osc/64 100 4 osc/64 101 5 osc/16 101 5 osc/16 110 6 osc/8 110 6 osc/8 111 7 osc/4 111 7 osc/4 unit:khz step4pb_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/2048 001 1 osc/1024 010 2 osc/512 011 3 osc/128 100 4 osc/64 101 5 osc/16 110 6 osc/8 111 7 osc/4 unit:khz note: bclk is clock frequency for booster circuit restriction -if some parameter of the register not use the regi ster need to be reserved. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value apb[2:0] step1b _sel[3:0] step2b _sel[2:0] ste4b _sel[2:0] step1pb _sel[3:0] step2pb _sel[2:0] ste4pb _sel[2:0] power on sequence 01h 00h 00h 00h 00h 00h 00h s/w reset 01h 00h 00h 00h 00h 00h 00h h/w reset 01h 00h 00h 00h 00h 00h 00h flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: apb[2:0] 2 nd parameter: step1b[3:0] & step2b[2:0] 3 rd parameter step2b[2:0] 4 th parameter step1pab2:0] & step2pb[2:0] 5 th parameter step4pb[2:0] ------------------ pwctr4 ( c3 h )
ST7787 ver. 1.7 2008.04.18 185 10.2.14 pwctr5 (c4h): power control 5 (in partial m ode/ full-colors) c4h pwctr5 (power control 5) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) pwctr5 0 1 - 1 1 0 0 0 1 0 0 (c4h) 1 st parameter 1 1 - 0 0 0 0 0 apc2 apc1 apc0 2 nd parameter 1 1 - step1c _sel3 step1c _sel2 step1c _sel1 step1c _sel0 0 step2c _sel2 step2c _sel1 step2c _sel0 00h 3 rd parameter 1 1 - - -- - - - step4c _sel2 step4c _sel1 step4c _sel0 4 th parameter 1 1 - - step1pc _sel2 step1pc _sel1 step1pc _sel0 - step2pc _sel2 step2pc _sel1 step2pc _sel0 5 th parameter 1 1 - - - - - - step4pc _sel2 step4pc _sel1 step4pc _sel0 note: - dont care description -set the amount of current in operational amplifier in partial mode/ full-colors. -adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. apc[2:0] amount of current in operational amplifier 000 0 operation of the operational amplifier stops 001 1 small 010 2 medium low 011 3 medium 100 4 medium high 101 5 large 110 6 reserved 111 7 reserved -set the booster circuit step-up cycle in partial m ode/ full-colors. note: bclk is clock frequency for booster circuit step1c_sel[3:0] step-up cycle in booster circuit 1 0000 0 osc/2048 0001 1 osc/1024 0010 2 osc/512 0011 3 osc/128 0100 4 osc/64 0101 5 osc/16 0110 6 osc/8 0111 7 osc/4 1000 8 osc/2048 1001 9 osc/1024 1010 10 osc/512 1011 11 osc/128 1100 12 osc/64 1101 13 osc/16 1110 14 osc/8 1111 15 osc/4 unit:khz note:while step1b_sel3 setting to 0, the charge p ump circuit is selected to single mode. on the co ntray to dual mode. step2c_sel[2:0] step-up cycle in booster circuit 2 step4c_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/2048 000 0 osc/2048 001 1 osc/1024 001 1 osc/1024 010 2 osc/512 010 2 osc/512 011 3 osc/128 011 3 osc/128 100 4 osc/64 100 4 osc/64 101 5 osc/16 101 5 osc/16 110 6 osc/8 110 6 osc/8 111 7 osc/4 111 7 osc/4
ST7787 ver. 1.7 2008.04.18 186 1. set the booster circuit step-up cycle during porch area in partial mode/ full-colors. step1pc_sel[2:0] step-up cycle in booster circuit 1 step2pc_sel[2:0] step-up cycle in booster circuit 2 000 0 osc/2048 000 0 osc/2048 001 1 osc/1024 001 1 osc/1024 010 2 osc/512 010 2 osc/512 011 3 osc/128 011 3 osc/128 100 4 osc/64 100 4 osc/64 101 5 osc/16 101 5 osc/16 110 6 osc/8 110 6 osc/8 111 7 osc/4 111 7 osc/4 unit:khz step4pc_sel[2:0] step-up cycle in booster circuit 4 000 0 osc/2048 001 1 osc/1024 010 2 osc/512 011 3 osc/128 100 4 osc/64 101 5 osc/16 110 6 osc/8 111 7 osc/4 unit:khz note: bclk is clock frequency for booster circuit restriction -if some parameter of the register not use the regi ster need to be reserved. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value apc[2:0] step1c _sel[3:0] step2c _sel[2:0] ste4c _sel[2:0] step1pc _sel[3:0] step2pc _sel[2:0] ste4pc _sel[2:0] power on sequence 01h 0bh 03h 03h 00h 00h 00h s/w reset 01h 0bh 03h 03h 00h 00h 00h h/w reset 01h 0bh 03h 03h 00h 00h 00h flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: apb[2:0] 2 nd parameter: step1b[3:0] & step2b[2:0] 3 rd parameter step2b[2:0] 4 th parameter step1pab2:0] & step2pb[2:0] 5 th parameter step4pb[2:0] ------------------ pwctr4 ( c4 h )
ST7787 ver. 1.7 2008.04.18 187 10.2.15 vmctr1 (c5h): vcom control 1 c5h vmctr1 (vcom control 1) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vmctr1 0 1 - 1 1 0 0 0 1 0 1 (c5h) 1 st parameter 1 1 - 0 vmh_r6 vmh_r5 vmh_r4 vmh_r3 vmh_r2 vmh_r1 vmh_r0 2 nd parameter 1 1 - 0 vmh _idmon6 vmh _idmon5 vmh _idmon4 vmh _idmon3 vmh _idmon2 vmh _idmon1 vmh _idmon0 3 rd parameter 1 1 - nvm0 --- ---- ---- ---- ---- ---- ---- note: - dont care description -set vcomh voltage in normal mode/full colors. vmh[6:0] vcomh vmh[6:0] vcomh vmh[6:0] vcomh vmh[6:0] vcomh 0000000 0 2.500 0011011 27 3.175 0110110 54 3.850 1010001 81 4.525 0000001 1 2.525 0011100 28 3.200 0110111 55 3.875 1010010 82 4.550 0000010 2 2.550 0011101 29 3.225 0111000 56 3.900 1010011 83 4.575 0000011 3 2.575 0011110 30 3.250 0111001 57 3.925 1010100 84 4.600 0000100 4 2.600 0011111 31 3.275 0111010 58 3.950 1010101 85 4.625 0000101 5 2.625 0100000 32 3.300 0111011 59 3.975 1010110 86 4.650 0000110 6 2.650 0100001 33 3.325 0111100 60 4.000 1010111 87 4.675 0000111 7 2.675 0100010 34 3.350 0111101 61 4.025 1011000 88 4.700 0001000 8 2.700 0100011 35 3.375 0111110 62 4.050 1011001 89 4.725 0001001 9 2.725 0100100 36 3.400 0111111 63 4.075 1011010 90 4.750 0001010 10 2.750 0100101 37 3.425 1000000 64 4.100 1011011 91 4.775 0001011 11 2.775 0100110 38 3.450 1000001 65 4.125 1011100 92 4.800 0001100 12 2.800 0100111 39 3.475 1000010 66 4.150 1011101 93 4.825 0001101 13 2.825 0101000 40 3.500 1000011 67 4.175 1011110 94 4.850 0001110 14 2.850 0101001 41 3.525 1000100 68 4.200 1011111 95 4.875 0001111 15 2.875 0101010 42 3.550 1000101 69 4.225 1100000 96 4.900 0010000 16 2.900 0101011 43 3.575 1000110 70 4.250 1100001 97 4.925 0010001 17 2.925 0101100 44 3.600 1000111 71 4.275 1100010 98 4.950 0010010 18 2.950 0101101 45 3.625 1001000 72 4.300 1100011 99 4.975 0010011 19 2.975 0101110 46 3.650 1001001 73 4.325 1100100 100 5.000 0010100 20 3.000 0101111 47 3.675 1001010 74 4.350 1100101 101 0010101 21 3.025 0110000 48 3.700 1001011 75 4.375 | 0010110 22 3.050 0110001 49 3.725 1001100 76 4.400 1111111 127 not permitted 0010111 23 3.075 0110010 50 3.750 1001101 77 4.425 0011000 24 3.100 0110011 51 3.775 1001110 78 4.450 0011001 25 3.125 0110100 52 3.800 1001111 79 4.475 0011010 26 3.150 0110101 53 3.825 1010000 80 4.500 -when the vcom circuit use vocmh + vcomac -the vcoml is generated from vcomh-vcomac -vcomh voltage also can be adjusted by vmh_idomon[6:0 ] register in idle mode/8 colors. vmh _idomon[6:0] vcomh vmh _idomon[6:0] vcomh vmh _idomon[6:0] vcomh vmh _idomon[6:0] vcomh 0000000 0 2.500 0011011 27 3.175 0110110 54 3.850 1010001 81 4.525 0000001 1 2.525 0011100 28 3.200 0110111 55 3.875 1010010 82 4.550 0000010 2 2.550 0011101 29 3.225 0111000 56 3.900 1010011 83 4.575 0000011 3 2.575 0011110 30 3.250 0111001 57 3.925 1010100 84 4.600 0000100 4 2.600 0011111 31 3.275 0111010 58 3.950 1010101 85 4.625 0000101 5 2.625 0100000 32 3.300 0111011 59 3.975 1010110 86 4.650 0000110 6 2.650 0100001 33 3.325 0111100 60 4.000 1010111 87 4.675 0000111 7 2.675 0100010 34 3.350 0111101 61 4.025 1011000 88 4.700 0001000 8 2.700 0100011 35 3.375 0111110 62 4.050 1011001 89 4.725 0001001 9 2.725 0100100 36 3.400 0111111 63 4.075 1011010 90 4.750 0001010 10 2.750 0100101 37 3.425 1000000 64 4.100 1011011 91 4.775 0001011 11 2.775 0100110 38 3.450 1000001 65 4.125 1011100 92 4.800 0001100 12 2.800 0100111 39 3.475 1000010 66 4.150 1011101 93 4.825 0001101 13 2.825 0101000 40 3.500 1000011 67 4.175 1011110 94 4.850 0001110 14 2.850 0101001 41 3.525 1000100 68 4.200 1011111 95 4.875 0001111 15 2.875 0101010 42 3.550 1000101 69 4.225 1100000 96 4.900 0010000 16 2.900 0101011 43 3.575 1000110 70 4.250 1100001 97 4.925 0010001 17 2.925 0101100 44 3.600 1000111 71 4.275 1100010 98 4.950 0010010 18 2.950 0101101 45 3.625 1001000 72 4.300 1100011 99 4.975 0010011 19 2.975 0101110 46 3.650 1001001 73 4.325 1100100 100 5.000 0010100 20 3.000 0101111 47 3.675 1001010 74 4.350 1100101 101 0010101 21 3.025 0110000 48 3.700 1001011 75 4.375 | 0010110 22 3.050 0110001 49 3.725 1001100 76 4.400 1111111 127 not permitted
ST7787 ver. 1.7 2008.04.18 188 0010111 23 3.075 0110010 50 3.750 1001101 77 4.425 0011000 24 3.100 0110011 51 3.775 1001110 78 4.450 0011001 25 3.125 0110100 52 3.800 1001111 79 4.475 0011010 26 3.150 0110101 53 3.825 1010000 80 4.500 -set vcomh voltage in normal mode/full colors. -when nvm0=1, vcomh voltage can be adjusted by vmh_r[ 6:0] register. -when nvm0=0, vcomh rogram will be setted by otp register value. restriction -if this register not using the register need be re served. -the deviation value of vcomh/vcoml between with measur ement and specification: max<=30mv -the deviation value of vcomac between with measurement and specification: max <=50mv register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value nvm0=0, vmh_r[6:0] nvm0=0, vmh_color8m[6:0] power on sequence 28h 28h s/w reset 28h 28h h/w reset 28h 28h flow chart le g e n d command parameter display action mode sequential transfer 1st parameter: vmh_r[6:0] 2nd parameter: vmh_color8m[6:0] 3 rd parameter nvm0 pwctr4 (c5h)
ST7787 ver. 1.7 2008.04.18 189 10.2.16 vmctr2 (c6h): vcom control 2 c6h vmctr2 (vcom control 2) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vmctr2 0 1 - 1 1 0 0 0 1 1 0 (c6h) 1 st parameter 1 1 - 0 0 vma5 vma4 vma3 vma2 vma1 vma0 2 nd parameter 1 1 - 0 0 vma _idmon5 vma _idmon 4 vma _idmon 3 vma _idmon 2 vma _idmon 1 vma _idmon 0 note: - dont care description -set vcomac voltage in normal mode/full colors. vma[5:0] vcomac vma[5:0] vcomac vma[5:0] vcomac 000000 0 4.000 010000 16 4.800 100000 32 5.600 000001 1 4.050 010001 17 4.850 100001 33 5.650 000010 2 4.100 010010 18 4.900 100010 34 5.700 000011 3 4.150 010011 19 4.950 100011 35 5.750 000100 4 4.200 010100 20 5.000 100100 36 5.800 000101 5 4.250 010101 21 5.050 100101 37 5.850 000110 6 4.300 010110 22 5.100 100110 38 5.900 000111 7 4.350 010111 23 5.150 100111 39 5.950 001000 8 4.400 011000 24 5.200 101000 40 6.000 001001 9 4.450 011001 25 5.250 101001 41 001010 10 4.500 011010 26 5.300 | 001011 11 4.550 011011 27 5.350 111111 63 not permitted 001100 12 4.600 011100 28 5.400 001101 13 4.650 011101 29 5.450 001110 14 4.700 011110 30 5.500 001111 15 4.750 011111 31 5.550 -set vcomac voltage in idle mode/8 colors. vma _idmon[5:0] vcomac vma _idmon[5:0] vcomac vma _idmon[5:0] vcomac 000000 0 4.000 010000 16 4.800 100000 32 5.600 000001 1 4.050 010001 17 4.850 100001 33 5.650 000010 2 4.100 010010 18 4.900 100010 34 5.700 000011 3 4.150 010011 19 4.950 100011 35 5.750 000100 4 4.200 010100 20 5.000 100100 36 5.800 000101 5 4.250 010101 21 5.050 100101 37 5.850 000110 6 4.300 010110 22 5.100 100110 38 5.900 000111 7 4.350 010111 23 5.150 100111 39 5.950 001000 8 4.400 011000 24 5.200 101000 40 6.000 001001 9 4.450 011001 25 5.250 101001 41 001010 10 4.500 011010 26 5.300 | 001011 11 4.550 011011 27 5.350 111111 63 not permitted 001100 12 4.600 011100 28 5.400 001101 13 4.650 011101 29 5.450 001110 14 4.700 011110 30 5.500 001111 15 4.750 011111 31 5.550 restriction -if this register not use the register need be rese rved. -the deviation value of vcomac between with measurement and specification: max <=50mv register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value lcm1, lcm0 = 01 tr lc type vma[6:0] lcm1, lcm0 = 01 tr lc type vma_idmon[5:0] power on sequence 06h 00h s/w reset 06h 00h h/w reset 06h 00h
ST7787 ver. 1.7 2008.04.18 190 flow chart le g e n d command parameter display action mode sequential transfer 1st parameter: vma[5:0] 2nd parameter: vma_idmon[5:0] ------------------ vmctr4 ( c6 h )
ST7787 ver. 1.7 2008.04.18 191 10.2.17 wrid1 (d0h): otp id1 set lcm version code d0h otp id1 set lcm version code inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) otp-read 0 1 - 1 1 0 1 0 0 0 0 (d0h) 1 st parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 description -otp id1 set the lcm version code restriction -if this register not using the register need be re served. -after adjust the c5h command(vcomh voltage) and c6h co mmand(vcomac voltage), vpp connect 7.5v. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 192 10.2.18 wrid2 (d1h): otp id2 set lcm version code d1h otp id2 set lcm version code inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) otp-read 0 1 - 1 1 0 1 0 0 0 1 (d1h) 1 st parameter 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 description -otp id2 set the lcm version code restriction -if this register not using the register need be re served. -after adjust the c5h command(vcomh voltage) and c6h command(vcomac v oltage), vpp connect 7.5v. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 193 10.2.19 wrid3 (d2h): otp id3 set project code d2h otp id3 set lcm version code inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) otp-read 0 1 - 1 1 0 1 0 0 1 0 (d2h) 1 st parameter 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 description -otp id3 set the project code restriction -if this register not using the register need be re served. -after adjust the c5h command(vcomh voltage) and c6h co mmand(vcomac voltage), vpp connect 7.5v. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 194 10.2.20 otp-load (deh): otp read command deh otp-load inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) otp-read 0 1 - 1 1 0 1 1 1 1 0 (deh) 1 st parameter 1 1 - 0 1 1 1 0 1 0 1 (75h) description -read otp value after otp rogramming, ic will download the otp value. if you change the vcomh register, you can execute deh command to re-download otp. restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence 75h s/w reset 75h h/w reset 75h flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 195 10.2.21 otp-prog (dfh): otp programimng command dfh otp-prog inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) otp-read 0 1 - 1 1 0 1 1 1 1 0 (dfh) 1 st parameter 1 1 - 0 1 1 1 0 1 0 1 (cah) 2 nd parameter 1 1 - 0 0 0 0 0 0 0 0 (00h) 3 rd parameter 1 1 - 1 0 1 0 1 0 1 0 (aah) 4rd parameter 1 1 - 1 0 1 0 0 1 0 1 (a5h) 5rd parameter 1 1 - 0 1 0 1 1 0 1 0 (5ah) description - otp download -set the vcomh voltage in normal mode/full colors an d idle mode/8 colors. -set the vcomac voltage in normal mode/full colors a nd idle mode/8 colors. restriction -if this register not using the register need be re served. -after adjust the c5h command(vcomh voltage) and c6h co mmand(vcomac voltage), vpp connect 7.5v. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence no change s/w reset no change h/w reset no change flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 196 10.2.22 gmctrp1 (e0h): gamma (+polarity) correcti on characteristics setting e0h gmctrp0 (gamma +polarity correction characteristic s setting) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gmctrp1 0 - 1 - 1 1 1 0 0 0 0 0 (e0h) 1 st parameter 1 - 1 - mva_en - - - rfp0[3] rfp0[2] rfp0[1] rfp0[0] 2 nd parameter 1 - 1 - - - - - pkp0[3] pkp0[2] pkp0[1] pkp0[0] 3 rd parameter 1 - 1 - - - - pkp1[4] pkp1[3] pkp1[2] pkp1[1] pkp1[0] 4 th parameter 1 - 1 - - - - pkp2[4] pkp2[3] pkp2[2] pkp2[1] pkp2[0] 5 th parameter 1 - 1 - - - - pkp3[4] pkp3[3] pkp3[2] pkp3[1] pkp3[0] 6 th parameter 1 - 1 - - - - pkp4[4] pkp4[3] pkp4]2] pkp4]1] pkp4]0] 7 th parameter 1 - 1 - - - - pkp5[4] pkp5[3] pkp5]2] pkp5]1] pkp5]0] 8 th parameter 1 - 1 - - - - pkp6[4] pkp6[3] pkp6[2] pkp6[1] pkp6[0] 9 th parameter 1 - 1 - - - - pkp7[4] pkp7[3] pkp7[2] pkp7[1] pkp7[0] 10 th parameter 1 - 1 - - - - - pkp8[3] pkp8[2] pkp8[1] pkp8[0] 11 th parameter 1 - 1 - - - - - rfp1[3] rfp1[2] rfp1[1] rfp1[0] 12 th parameter 1 - 1 - - - - - - osp1[2]osp1[1]osp1[0] 13 th parameter 1 - 1 - - - - osp0[4] osp0[3]osp0[2]osp0[1]osp0[0] description -when mva_en=1, the gamma correction select to mva type -when mva_en=0, the gamma correction dont select to mva type register group negative polarity set-up contents high level adjustment rfp0[3:0] variable resistor v rhp pkp0[3:0] the voltage of grayscale number 3 is selected by the 16 to 1 selector pkp1[4:0] the voltage of grayscale number 6 is selected by the 32 to 1 selector pkp2[4:0] the voltage of grayscale number 11 is selected by the 32 to 1 selector pkp3[4:0] the voltage of grayscale number 20 is selected by the 32 to 1 selector pkp4[4:0] the voltage of grayscale number 31 is selected by the 32 to 1 selector pkp5[4:0] the voltage of grayscale number 43 is selected by the 32 to 1 selector pkp6[4:0] the voltage of grayscale number 52 is selected by the 32 to 1 selector pkp7[4:0] the voltage of grayscale number 57 is selected by the 32 to 1 selector pkp8[3:0] the voltage of grayscale number 60 is selected by the 16 to 1 selector rfp1[3:0] the voltage of grayscale number 1 is selected by the 16 to 1 selector mid level adjustment osp1[2:0] the voltage of grayscale number 62 is selected by the 7 to 1 selector low level adjustment osp0[4:0] variable resistor vr lp restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes
ST7787 ver. 1.7 2008.04.18 197 default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: | 13 th parameter ------------------ gmctrp1 ( e0 h )
ST7787 ver. 1.7 2008.04.18 198 10.2.23 gmctrn1 (e1h): gamma (-polarity) correcti on characteristics setting e1h gmctrp0 (gamma +polarity correction characteristic s setting) inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gmctrp1 0 - 1 - 1 1 1 0 0 0 0 0 (e1h) 1 st parameter 1 - 1 - - - - - rfn0[3] rfn0[2] rfn0[1] rfn0[0] 2 nd parameter 1 - 1 - - - - - pkn0[3] pkn0[2] pkn0[1] pkn0[0] 3 rd parameter 1 - 1 - - - - pkn1[4] pkn1[3] pkn1[2] pkn1[1] pkn1[0] 4 th parameter 1 - 1 - - - - pkn2[4] pkn2[3] pkn2[2] pkn2[1] pkn2[0] 5 th parameter 1 - 1 - - - - pkn3[4] pkn3[3] pkn3[2] pkn3[1] pkn3[0] 6 th parameter 1 - 1 - - - - pkn4[4] pkn4[3] pkn4]2] pkn4]1] pkn4]0] 7 th parameter 1 - 1 - - - - pkn5[4] pkn5[3] pkn5]2] pkn5]1] pkn5]0] 8 th parameter 1 - 1 - - - - pkn6[4] pkn6[3] pkn6[2] pkn6[1] pkn6[0] 9 th parameter 1 - 1 - - - - pkn7[4] pkn7[3] pkn7[2] pkn7[1] pkn7[0] 10 th parameter 1 - 1 - - - - - pkn8[3] pkn8[2] pkn8[1] pkn8[0] 11 th parameter 1 - 1 - - - - - rfn1[3] rfn1[2] rfn1[1] rfn1[0] 12 th parameter 1 - 1 - - - - - - osn1[2]osn1[1]osn1[0] 13 th parameter 1 - 1 - - - - osn0[4] osn0[3] osn0[2]osn0[1]osn0[0] description register group negative polarity set-up contents high level adjustment rfn0[3:0] variable resistor v rhn pkn0[3:0] the voltage of grayscale number 3 is selected by the 16to 1 selector pkn1[4:0] the voltage of grayscale number 6 is selected by the 32 to 1 selector pkp2[4:0] the voltage of grayscale number 11 is selected by the 32 to 1 selector pkn3[4:0] the voltage of grayscale number 20 is selected by the 32 to 1 selector pkn4[4:0] the voltage of grayscale number 31 is selected by the 32 to 1 selector pkn5[4:0] the voltage of grayscale number 43 is selected by the 32 to 1 selector pkn6[4:0] the voltage of grayscale number 52 is selected by the 32 to 1 selector pkn7[4:0] the voltage of grayscale number 57 is selected by the 64 to 1 selector pkn8[3:0] the voltage of grayscale number 60 is selected by the 16 to 1 selector rfn1[3:0] the voltage of grayscale number 1 is selected by the 16 to 1 selector mid level adjustment osn1[2:0] the voltage of grayscale number 62 is selected by the 7 to 1 selector low level adjustment osn0[4:0] variable resistor vr ln restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed
ST7787 ver. 1.7 2008.04.18 199 flow chart le g e n d command parameter display action mode sequential transfer 1 st parameter: | 13 th parameter gmctrp1 ( e1 h )
ST7787 ver. 1.7 2008.04.18 200 10.2.24 vcom multi_mode (fbh): deh otp-load inst / para d/cx wrx rdx d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vcom_multi_mode 0 1 - 1 1 1 1 1 0 1 1 (fbh) 1 st parameter 1 1 - 0 1 vcom _multi_mode 1 1 1 1 1 description -vcom multi_mode for power saving, please set the vcom_multi_mode=1. restriction -if this register not using the register need be re served. register availability status availability normal mode on, idle mode ooff, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode off, idle mode on, sleep out yes sleep in no default status default value power on sequence 7fh s/w reset 7fh h/w reset 7fh flow chart le g e n d command parameter display action mode sequential transfer
ST7787 ver. 1.7 2008.04.18 201 11. display module default position the default position of the display is always as fo llow, when madctls (36h) parameter is 00h. the 1 s t pixel on the display. t h i s i s a l so t h e 1 st a ccess lo cat i o n r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b d i spla y dr i v er r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b
ST7787 ver. 1.7 2008.04.18 202 12. power structure 12.1. driver ic operating voltages specification vdd=(2.45v3.0v) agnd=0v chargepump vgh(12v~16.5v) avdd(4.9v~6.6v) gvdd(3.0v~5.0v) vcomh(2.5v~5.0v) internalreference voltage vcl(3.3v~2.2v) vgl(5v~14v) vcoml(2.5v~0v) remark 1. avdd supply to all power source (exclude vgh, vg l) 2. source output range: 0.1v ~ avdd-0.1v 3. linear range: 0.2v ~ avdd-0.2v (for all output voltage, but exclude vgh, vgl) 4. above operating voltages is min range.
ST7787 ver. 1.7 2008.04.18 203 12.2 power booster circuit 12.2.1 vci1 generate from vdd regulator boost 1 (x2)vci1 set-yp 1 bt[2:0] dc[2:0] or dct[2:0] reference voltage generator boost 2,3,4 (x4, x5, x6)vci1 (x-2, x-4, x-5)vci1 (x-1)vci1 set-up 2,3,4 bt[2:0] dc[2:0] or dct[2:0] gray reference circuit block (gamma) source output circuit block gate output cirrect block vref vref vref vref vci1 vci1 avdd avdd agnd vdd vcl vref vdd c vdd c vci1 c11 c12 c avdd vgh vgl vcl c21 c22 c23 c vgh c vgl c vcl avdd agnd s1 | s720 avdd agnd gvdd c vci1 vgh vgl vddi c vddi vrh [4:0} vmh[6:0} + vmof[6:0] vc [2:0} c vml c vmh vcomh vcoml vcom g1 | g320 vmh[6:0} + vmof[6:0] agnd fig.12.2.1powerboosterstructure(1)
ST7787 ver. 1.7 2008.04.18 204 12.2.2 external components connection pad name connection rated (min) voltage typical capacitance value vddi vddi (logic power) 10.0v 1.0 uf vdd vdd (analog power) 10.0v 1.0 uf vcc connect to capacitor (max 3v): vcc -------||------- - gnd 10.0v 1.0 uf agnd analog ground (connect to gnd) dgnd digital ground (connect to gnd) c23p, c23n connect to capacitor: c23p -------||--------c23n 25.0v 1.0 uf c22p, c22n connect to capacitor: c22p -------||--------c22n 25.0v 1.0 uf c21p, c22n connect to capacitor: c21p -------||--- -----c21n 10.0v 1.0 uf c12p, c12n connect to capacitor: c12p -------||--------c12n 10.0v 1.0 uf c11p, c11n connect to capacitor: c11p -------||--------c11n 10.0v 1.0 uf avdd connect to capacitor: avdd -------||-------- gnd 10.0v 1.0 uf vci1 connect to capacitor: avdd -------||-------- gnd 10.0v 1.0 uf vgh connect to capacitor: vgh -------||-------- gnd 25.0v 1.0 uf vgl connect to capacitor: vgl -------||-------- gnd 25.0v 1.0 uf vcl connect to capacitor: vcl -------||-------- gnd 10.0v 1.0 uf vref connect to capacitor: vref -------||-------- gnd 10.0v 1.0 uf gvdd connect to capacitor: gvdd -------||-------- gnd 10.0v 1.0 uf vcomh connect to capacitor: vcomh-------||--------- gnd 10.0v 1.0 uf vcoml connect to capacitor: vcoml -------||-------- gnd 10.0v 1.0 uf vc1s connect to capacitor: vc1s -------||-------- gnd 10v 1.0uf vgl connect to schottky diode: vgl -------.|-------- gn d 30v schottky diode
ST7787 ver. 1.7 2008.04.18 205 13. gamma structure 13.1 structure of grayscale amplifier the structure of grayscale amplifier is shown as be low. 13 voltage levels (vin0-vin12) between gvdd an d vgs are determined by the high/ mid/ low level adjustment r egisters. each mid-adjustment level is split into 6 4 levels again by the internal ladder resistor network. as a result, gray scale amplifier generates 64 voltage levels ranging from v0 to v63 and outputs one of 64 levels. positive frame negative frame gvdd 0 ~ 2 2 . 5 r rf0p[3:0] 0~ 30 r rf1p[3:0] pkp0[3:0] pkp1[4:0] pkp2[4:0] pkp3[4:0] pkp4[4:0] pkp5[4:0] pkp6[4:0] pkp7[4:0] pkp8[3:0] 0 ~ 2 8 r os1p[2:0] 0 ~ 2 2 . 5 r os0p[3:0] 30r 30r v0 v1 v3 v6 v11 v20 v31 v43 v52 v57 v60 v62 v63 step : 2r step : 1.5r step : 4r step : 1.5r 184r gvdd 0 ~ 2 2 . 5 r os0n[3:0] 0 ~ 2 8 r os1n[2:0] pkn0[3:0] pkn1[4:0] pkn2[4:0] pkn3[4:0] pkn4[4:0] pkn5[4:0] pkn6[4:0] pkn7[4:0] pkn8[3:0] 0 ~ 3 0 r rf1n[3:0] 0 ~ 2 2 . 5 r rf0n[3:0] 30r 30r v63 v62 v1 v0 v60 v57 v52 v43 v31 v20 v11 v6 v3 step : 4r step : 1.5r step : 2r step : 1.5r
ST7787 ver. 1.7 2008.04.18 206 13.2 gamma voltage formula (positive/ negative pola rity) grayscale voltage formula(positive) voltage formula(negative) 0 vinp0 vinn 0 1 vinp1 vinn 1 2 v1-(v1-v3)*(16/30) v1-(v1-v3)*(17/30) 3 vin2 vinn 2 4 v3-(v3-v6)*(21/60) v3-(v3-v6)*(12/30) 5 v3-(v3-v6)*(41/60) v3-(v3-v6)*(22/30) 6 vinp3 vinn 3 7 v6-(v6-v11)*(13/60) v6-(v6-v11)*(9/40) 8 v6-(v6-v11)*(26/60) v6-(v6-v11)*(17/40) 9 v6-(v6-v11)*(38/60) v6-(v6-v11)*(25/40) 10 v6-(v6-v11)*(49/60) v6-(v6-v11)*(33/40) 11 vinp4 vinn 4 12 v11-(v11-v20)*(8/60) v11-(v11-v20)*(4/36) 13 v11-(v11-v20)*(16/60) v11-(v11-v20)*(8/36) 14 v11-(v11-v20)*(24/60) v11-(v11-v20)*(12/36) 15 v11-(v11-v20)*(31/60) v11-(v11-v20)*(16/36) 16 v11-(v11-v20)*(38/60) v11-(v11-v20)*(20/36) 17 v11-(v11-v20)*(44/60) v11-(v11-v20)*(24/36) 18 v11-(v11-v20)*(50/60) v11-(v11-v20)*(28/36) 19 v11-(v11-v20)*(55/60) v11-(v11-v20)*(32/36) 20 vinp5 vinn 5 21 v20-(v20-v31)*(6/60) v20-(v20-v32)*(5/60) 22 v20-(v20-v31)* (12/60) v20-(v20-v32)* (10/60) 23 v20-(v20-v31)* (18/60) v20-(v20-v32)* (15/60) 24 v20-(v20-v31)* (24/60) v20-(v20-v32)* (20/60) 25 v20-(v20-v31)* (30/60) v20-(v20-v32)* (25/60) 26 v20-(v20-v31)* (35/60) v20-(v20-v32)* (30/60) 27 v20-(v20-v31)* (40/60) v20-(v20-v32)* (35/60) 28 v20-(v20-v31)* (45/60) v20-(v20-v32)* (40/60) 29 v20-(v20-v31)* (50/60) v20-(v20-v32)* (45/60) 30 v20-(v20-v31)* (55/60) v20-(v20-v32)* (50/60) 31 vinp6 v20-(v20-v32)* (55/60) 32 v31-(v31-v43)*(5/60) vinn6 33 v31-(v31-v43)*(10/60) v32-(v32-v43)*(5/60) 34 v31-(v31-v43)*(15/60) v32-(v32-v43)*(10/60) 35 v31-(v31-v43)*(20/60) v32-(v32-v43)*(15/60) 36 v31-(v31-v43)*(25/60) v32-(v32-v43)*(20/60) 37 v31-(v31-v43)*(30/60) v32-(v32-v43)*(25/60) 38 v31-(v31-v43)*(35/60) v32-(v32-v43)*(30/60) 39 v31-(v31-v43)*(40/60) v32-(v32-v43)*(36/60) 40 v31-(v31-v43)*(45/60) v32-(v32-v43)*(42/60) 41 v31-(v31-v43)*(55/60) v31-(v31-v43)*(48/60) 42 v31-(v31-v43)*(60/60) v31-(v31-v43)*(54/60) 43 vinp7 vinn 7 44 v43-(v43-v52)*(2/18) v43-(v43-v52)*(5/60) 45 v43-(v43-v52)*(4/18) v43-(v43-v52)*(10/60) 46 v43-(v43-v52)*(6/18) v43-(v43-v52)*(16/60) 47 v43-(v43-v52)*(8/18) v43-(v43-v52)*(22/60) 48 v43-(v43-v52)*(10/18) v43-(v43-v52)*(29/60) 49 v43-(v43-v52)*(12/18) v43-(v43-v52)*(36/60) 50 v43-(v43-v52)*(14/18) v43-(v43-v52)*(44/60) 51 v43-(v43-v52)*(16/18) v43-(v43-v52)*(52/60) 52 vinp8 vinn 8 53 v52-(v52-v57)*(7/40) v52-(v52-v57)*(11/60) 54 v52-(v52-v57)*(15/40) v52-(v52-v57)*(22/60)
ST7787 ver. 1.7 2008.04.18 207 55 v52-(v52-v57)*(23/40) v52-(v52-v57)*(34/60) 56 v52-(v52-v57)*(31/40) v52-(v52-v57)*(47/60) 57 vinp9 vinn 9 58 v57-(v57-v60)*(8/30) v57-(v57-v60)*(19/60) 59 v57-(v57-v60)*(18/30) v57-(v57-v60)*(39/60) 60 vinp10 vinn 10 61 v60-(v60-v62)*(13/30) v60-(v60-v62)*(14/30) 62 vinp11 vinn 11 63 vinp12 vinn12
ST7787 ver. 1.7 2008.04.18 208 14. example connection with panel direction and dif ferent resolution 14.1 application of connection with panel direction case 1: (this is default case) - 1 st pixel is at left top of the panel - rgb filter order = r g b case 2: - 1 st pixel is at left top of the panel - rgb filter order = b g r - direction default setting (h/w) smx = 0 smy = 0 srgb = 1 s1 = filter b s2 = filter g s3 = filter r - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 01h 02h ---- ---- ---- edh eeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 g 320 g 320 g 320 g 320 ST7787 (bump down) g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 00h efh 1 11 1 st stst st pixel pixel pixel pixel ic (bump down) lc d front side cf glass tft glass - direction default setting (h/w) smx = 0 smy = 0 srgb = 0 s1 = filter r s2 = filter g s3 = filter b - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 01h 02h ---- ---- ---- edh eeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 g 320 g 320 g 320 g 320 ST7787 (bump down) g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 00h efh 1 11 1 st stst st pixel pixel pixel pixel ic (bump down) lcd front side cf glass tft glass
ST7787 ver. 1.7 2008.04.18 209 case 3: - 1 st pixel is at righ bottom of the panel - rgb filter order = r g b case 4: - 1 st pixel is at righ bottom of the panel - rgb filter order = b g r - direction default setting (h/w) smx = 1 smy = 1 srgb = 1 s1 = filter b s2 = filter g s3 = filter r - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 01h 02h ---- ---- ---- edh eeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 00h efh g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 g 320 g 320 g 320 g 320 ST7787 (bump down) 1 11 1 st stst st pixel pixel pixel pixel ic (bump down) lcd front side cf glass tft glass - direction default setting (h/w) smx = 1 smy = 1 srgb = 0 s1 = filter r s2 = filter g s3 = filter b - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 01h 02h ---- ---- ---- edh eeh g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 00h efh g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 g 320 g 320 g 320 g 320 ST7787 (bump down) 1 11 1 st stst st pixel pixel pixel pixel ic (bump down) lcd front side cf glass tft glass
ST7787 ver. 1.7 2008.04.18 210 14.2 application of connection with different resol ution ram size=240 x 320 x 18-bits (used) display size = 240 rgb x 320 1). example for smx=smy=0 2). example for smx=smy=1 02h --- --- --- --- --- eeh 00h 01h 02h | | | | | | | | | | | | | 13eh 13fh 00h efh g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) (0,0) (0,0) (0,0) (0,0) (239,319) (239,319) (239,319) (239,319) g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 d2 -- -- -- -- -- d239 g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 g 320 g 320 g 320 g 320 ST7787 (bump down) g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 d1 d240 1 11 1 st stst st p ixel p ixel p ixel p ixel (0,0) (0,0) (0,0) (0,0) (239,319) (239,319) (239,319) (239,319) - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv - direction default setting (h/w) smx = 1 smy = 1 srgb = 0 g 319 g 319 g 319 g 319 s 720 s 720 s 720 s 720 d2 -- -- -- -- -- d239 g1 g2 g3 | g4 | | | | | | | | | | | | | | | | | | | | g317 | g318 g319 g320 d1 d240 g 1 g 1g 1 g 1 s 1 s 1s 1 s 1 g 2 g 2g 2 g 2 g 320 g 320 g 320 g 320 ST7787 (bump down) 1 11 1 st stst st pixel pixel pixel pixel (0,0) (0,0) (0,0) (0,0) (239,319) (239,319) (239,319) (239,319) 02h --- --- --- --- --- eeh 00h 01h 02h | | | | | | | | | | | | | 13eh 13fh 00h efh g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) g r a m s i z e (240x 320x 18-b i t s ) (0,0) (0,0) (0,0) (0,0) (239,319) (239,319) (239,319) (239,319) - display direction control (s/w) - x-mirror control by mx - y-mirror control by my - xy-exchange control by mv - direction default setting (h/w) smx = 0 smy = 0 srgb = 0
ST7787 ver. 1.7 2008.04.18 211 14.3 microprocessor interface applications 14.3.1 8080-seriers mcu + spi interface (rcm = 00 , p68=0, im2=1) 14.3.1.1 8080-series mcu interface for 8-bits data bus (im1, im0=00) 14.3.1.2 8080-series mcu interface for 16-bits data bus (im1, im0=01) note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d7 to d1 d0 0 0 01 im2 resx te scl sda d/cx wrx rdx d7 to d1 d0 d15 to d8 d17 to d16 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.1.2 8080-series mcu interface for 16-bits data bus d15 to d8 note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d7 to d1 d0 0 0 0 00 im2 resx te scl sda d/cx wrx rdx d7 to d1 d0 d15 to d8 d17 to d16 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.1.1 8080-series mcu interface for 8-bits data bus
ST7787 ver. 1.7 2008.04.18 212 14.3.1.3 8080-series mcu interface for 9-bits data bus (im1, im0=10) 14.3.1.4 8080-series mcu interface for 18-bits data bus (im1, im0=11) note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d8 to d1 d0 0 0 0 10 im2 resx te scl sda d/cx wrx rdx d8 to d1 d0 d15 to d9 d17 to d16 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.1.3 8080-series mcu interface for 9-bits data bus note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d7 to d1 d0 0 11 im2 resx te scl sda d/cx wrx rdx d7 to d1 d0 d 17 to d8 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.1.4 8080-series mcu interface for 18-bits data bus d17 to d8
ST7787 ver. 1.7 2008.04.18 213 14.3.2 6800-seriers mcu + spi interface (rcm = 00 , p68=1, im2=1) 14.3.2.1 6800-series mcu interface for 8-bits data bus (im1, im0=00) 14.3.2.2 6800-series mcu interface for 16-bits data bus (im1, im0=01) note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd ho st ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d7 to d1 d0 0 1 01 im2 resx te scl sda d/cx r/wx e d7 to d1 d0 d15 to d8 d17 to d16 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.2.2 6800-series mcu interface for 16-bits data bus d15 to d8 note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d7 to d1 d0 0 0 1 00 im2 resx te scl sda d/cx r/wx e d7 to d1 d0 d15 to d8 d17 to d16 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.2.1 6800-series mcu interface for 8-bits data bus
ST7787 ver. 1.7 2008.04.18 214 14.3.2.3 6800-series mcu interface for 9-bits data bus (im1, im0=10) 14.3.2.4 6800-series mcu interface for 18-bits data bus (im1, im0=11) note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx) rdx(e) d8 to d1 d0 0 0 1 10 im2 resx te scl sda d/cx r/wx e d8 to d1 d0 d15 to d9 d17 to d16 p68 im1 ,im0 im2 vs, hs, de plck fig. 14.3.2.3 6800-series mcu interface for 9-bits data bus note: rcm = 0x im2=0, spi i/f im2=1, mcu i/f dgnd host ST7787 resx te d/cx(scl) wrx(r/wx ) rdx(e) d7 to d1 d0 1 11 im2 resx te scl sda d /cx r/wx e d7 to d1 d0 d17 to d8 p68 im1,im0 im2 vs, hs, de plck fig. 14.3.2.4 6800-series mcu interface for 18-bits data bus d17 to d8
ST7787 ver. 1.7 2008.04.18 215 14.3.3 rgb interface (rcm = 1) 14.3.3.1 rgbinterface for 6-bits data width fig. 14.3.3.1 rgb interface for 6-bits data width 14.3.3.2 rgbinterface for 16-bits data width fig. 14.3.3.2 rgb interface for 16-bits data width
ST7787 ver. 1.7 2008.04.18 216 14.3.3.3 rgbinterface for 18-bits data width fig. 14.3.3.3 rgb interface for 18-bits data width
ST7787 ver. 1.7 2008.04.18 217 11. revise history ST7787 serial specification revision history version date description page 0.5b 2007/02/06 add timing value 1.0 2007/3/2 modify power on and off sequence 1.0 2007/3/2 add fbh command 1.1 2007/06/14 modify the operation temperature range modify the command 3ah modify gamma structure p2 p157 p206 1.2 2007/9/6 removed the description of 4-line p22 1.3 2007/9/11 modify 3spi interface description modify ramhd typo to ramrd modify vipf[3:0] typo p34 p142 p157 1.4 2007/10/2 modify the description of power on/off sequence(9.1 5) remove table 9.17.3.1 reset input timing(9.17.3) modify the figure of reset timing (9.17.3) modify the waiting time of swreset to 120ms(10.1.2) modify the waiting time of slpout to 120ms(10.1.12) p91 p96 p96 p111 p124 1.5 2007/11/26 modify the description of command e0h & e1h modify power consumption iddi (unit) modify operation temperature range modify rgb interface application circuit p196, p198 p29 p27~p30, p32~33 p215~216 1.6 2008/3/6 modify power on sequence on rgb mode 2 fro m vddi vdd to vdd vddi(9.9.6.4) modify power off sequence on rgb mode 2 from vddi vdd to vdd vddi(9.9.6.5) p73 p74 1.7 2009/4/18 modify wrx level on rgb mode from vddi or dgnd to vddi only modify scl signal on spi mode during proch area fro m clock to hi level p22,p215,p216 p40,p44

▲Up To Search▲

Price & Availability of ST7787

	To Download ST7787 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .